atf280e ATMEL Corporation, atf280e Datasheet - Page 16
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atf280e
Manufacturer Part Number
atf280e
Description
Rad Hard Reprogrammable Fpga
Manufacturer
ATMEL Corporation
Datasheet
1.ATF280E.pdf
(45 pages)
- Current page: 16 of 45
- Download datasheet (2Mb)
4.2
The Core Cell
The following figure depicts the ATF280E cell which is a highly configurable logic block based
around two 3-input LUTs (8 x 1 ROM), and which can be combined to produce one 4-input LUT.
This means that any cell can implement two functions of 3 inputs or one function of 4 inputs.
Figure 4-3.
ATF280E Core Cell
Every cell includes a register element, a D-type flip-flop, with programmable clock and reset
polarities. The initialization of the register is also programmable. It can be either SET or RESET.
The flip-flop can be used to register the output of one of the LUT. It can also be exploited in con-
junction with the feedback path element to implement a complete ripple counter stage in a single
cell. The registered or unregistered output of each LUT can be feedback within the cell and
treated as another input (Feedback signal in Figure 3). This allows, for example, a single counter
stage to be implemented within one cell without using external routing resources for the feed-
back connection.
There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the “front end” of
the cell. This AND gate is an important feature in the implementation of efficient array multipliers
as the product and carry terms can both be generated within a single logic cell.
The cell flexibility makes the ATF280E architecture well suited for most of the digital design
application areas.
ATF280E
16
7750A–AERO–07/07
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