adsp-2186lbst-1602 Analog Devices, Inc., adsp-2186lbst-1602 Datasheet
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adsp-2186lbst-1602
Manufacturer Part Number
adsp-2186lbst-1602
Description
Dsp Microcomputer
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-2186LBST-1602.pdf
(48 pages)
PERFORMANCE FEATURES
Up to 19 ns instruction cycle time, 52 MIPS sustained
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
Up to 160K bytes of on-chip RAM, configured
Dual-purpose program memory for both instruction and
Independent ALU, multiplier/accumulator, and barrel shifter
2 independent data address generators
Powerful program sequencer provides zero overhead loop-
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
ICE-Port is a trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
performance
instruction cycle
pation with 400 CLKIN cycle recovery from power-down
condition
syntax), with instruction set extensions
Up to 32K words program memory RAM
Up to 32K words data memory RAM
data storage
computational units
ing conditional instruction execution
DATA ADDRESS
GENERATORS
DAG1
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG2
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
MAC
SEQUENCER
PROGRAM
SHIFTER
PROGRAM MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY ADDRESS
Figure 1. Functional Block Diagram
DATA MEMORY DATA
32K
PROGRAM
MEMORY
UP TO
24-BIT
SPORT0
POWER-DOWN
SERIAL PORTS
MEMORY
CONTROL
32K
SPORT1
MEMORY
UP TO
DATA
16-BIT
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYSTEM INTERFACE FEATURES
16-bit internal DMA port for high-speed access to on-chip
4M-byte memory interface for storage of data tables and pro-
8-bit DMA to byte memory for transparent program and data
Programmable memory strobe and separate I/O memory
Programmable wait state generation
2 double-buffered serial ports with companding hardware
Automatic booting of on-chip program memory from byte-
6 external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port emulator interface supports debugging in final
memory (mode selectable)
gram overlays (mode selectable)
memory transfers (mode selectable)
space permits “glueless” system design
and automatic data buffering
wide external memory, for example, EPROM, or through
internal DMA Port
systems
TIMER
PROGRAMMABLE
FLAGS
AND
I/O
©2008 Analog Devices, Inc. All rights reserved.
DSP Microcomputer
FULL MEMORY MODE
CONTROLLER
HOST MODE
EXTERNAL
EXTERNAL
EXTERNAL
BYTE DMA
INTERNAL
ADDRESS
DATA
DATA
PORT
OR
BUS
BUS
BUS
DMA
www.analog.com