adsp-21020 Analog Devices, Inc., adsp-21020 Datasheet
adsp-21020
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adsp-21020 Summary of contents
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... Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the ADSP-21020 has instruction cycle time. With a high- performance on-chip instruction cache, the ADSP-21020 can execute every instruction in a single cycle. The ADSP-21020 features: • ...
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... ADSP-21xxx code within the hardware configuration described by a system architecture file. It flags illegal operations and supports full symbolic disassembly. It provides an easy-to-use, window oriented, graphical user interface that is identical to the one used by the ADSP-21020 EZ-ICE Emulator. Commands are accessed from pull-down menus with a mouse. • ...
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... REGISTER FILE SHIFTER Figure 1. ADSP-21020 Block Diagram of the ADSP-21020 allow the following nine data transfers to be performed every cycle: • Off-chip read/write of two operands to or from the register file • Two operands supplied to the ALU • Two operands supplied to the multiplier • ...
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... ADSP-21020 unless it requires a memory access from the affected interface. The three-state controls make it easy for an external cache controller to hold the ADSP-21020 off the bus while it updates an external cache memory. JTAG Test and Emulation Support The ADSP-21020 implements the boundary scan testing provisions specified by IEEE Standard 1149 ...
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... JTAG port. PIN DESCRIPTIONS This section describes the pins of the ADSP-21020. When groups of pins are identified with subscripts, e.g. PMD highest numbered pin is the MSB (in this case, PMD identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI, and TRST) ...
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... No Connect. No Connects are reserved pins that must be left open and unconnected. INSTRUCTION SET SUMMARY The ADSP-21020 instruction set provides a wide variety of programming capabilities. Every instruction assembles into a single word and can execute in a single processor cycle. Multifunction instructions enable simultaneous multiplier and ALU operations, as well as computations executed in parallel with data transfers ...
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... PM(<data6>, Ic) ureg1 = ureg2 ; | | = dreg ; DM(Ia, Mb PM(Ic, Md dreg = DM(Ia, Mb PM(Ic, Md MODIFY (Ia, Mb MODIFY (Ic, Md) <addr24> (PC, <reladdr6> DB, LA (PC, <reladdr6> (Md, Ic (PC, <reladdr6> DB, LA (PC, <reladdr6> compute ; <addr24> UNTIL LCE ; | | ( <PC <reladdr24>)( UNTIL LCE ; | | , DO <addr24> UNTIL termination ; | | | ( , DO (PC, <reladdr24>) –7– ADSP-21020 | ; | | ) ; | | | ) , compute ; | | ...
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... ADSP-21020 IMMEDIATE MOVE INSTRUCTIONS 14a. DM(<addr32>) = ureg ; PM(<addr24>) 14b. ureg = DM(<addr32>) ; PM(<addr24>) 15a. DM(<data32>, Ia) = ureg; PM(< data24>, Ic) 15b. ureg = DM(<data32>, Ia) ; PM(<data24>, Ic) 16. DM(Ia, Mb) = <data32>; PM(Ic, Md) 17. ureg = <data32>; MISCELLANEOUS INSTRUCTIONS 18. BIT SET sreg <data32>; CLR TGL TST XOR 19a. MODIFY (Ia, <data32>)|; (Ic, <data32>)| 19b. BITREV (Ia, < ...
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... AND FIX FIX XOR FLOAT NOT FLOAT RECIPS RSQRTS COPYSIGN Fy Rn, Rx, Ry R15–R0; register file location, fixed-point Fn, Fx, Fy F15–F0; register file location, floating point –9– ADSP-21020 ...
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... ADSP-21020 Table V. Multiplier Compute Operations MRF = MRB = MRF + MRB + MRF = MRF + MRB = MRB Rn = SAT MRF (SI SAT MRB (UI) MRF = SAT MRF (SF) MRB = SAT MRB (UF) MRF = 0 MRB ...
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... DAG 1 circular buffer 7 overflow 12 0x60 DAG 2 circular buffer 15 overflow 13 0x68 Reserved 14 0x70 Timer=0 (low priority option) 15 0x78 Fixed-point overflow 16 0x80 Floating-point overflow 17 0x88 Floating-point underflow 18 0x90 Floating-point invalid operation 19–23 0x98-0xB8 Reserved 24–31 0xC0–OxF8 User software interrupts *Nonmaskable –11– ADSP-21020 ...
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... I (typical) = 115 mA. See “Power Dissipation” for calculation of external (EVDD) supply current for total supply current. DDIN DDIN 8 Applies to IVDD pins. Idle refers to ADSP-21020 state of operation during execution of the IDLE instruction. 9 Guaranteed but not tested. 10 Applies to all signal pins. ...
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... CLKIN (not including clock oscillator start-up time Specification only applies in cases where multiple ADSP-21020 processors are required to execute in program counter lock-step (all processors start execution at location 8 in the same cycle). See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for reset sequence information. CLKIN RESET REV ...
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... Meeting setup and hold guarantees interrupts will be latched in that cycle. Meeting the pulse width is not necessary if the setup and hold is met. Likewise, meeting the setup and hold is not necessary if the pulse width is met. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for interrupt servicing informa- tion ...
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... NOTES * – Flag inputs meeting these setup and hold times will affect conditional operations in the next instruction cycle. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for additional flag servicing information DM. CLKIN t DFOE FLAG3-0 ...
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... CK Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE. Buses are not granted until completion of current memory access. See the Memory Interface chapter of the ADSP-21020 User’s Manual for BG, BR cycle relationships. CLKIN t t HBR ...
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... Min Max Min Max Min –2 – STS t t DTSD DSTS t DTSAE Figure 9. External Memory Three-State Control –17– ADSP-21020 K Grade 33.3 MHz Frequency Dependency* Max DT 7DT DT/2 –5 DT STS Unit ...
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... ADSP-21020 Memory Read Parameter Timing Requirement: t Address, Select to Data Valid DAD t xRD Low to Data Valid DRLD t Data Hold from Address, Select HDA t Data Hold from xRD High HDRH t xACK Delay from Address DAAK t xACK Delay from xRD Low DRAK t xACK Setup before CLKIN High ...
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... CLKIN ADDRESS, SELECT t DAP DMPAGE, PMPAGE t DCKRL DMRD, PMRD DATA DMACK, PMACK DMWR, PMWR REV DARL RW t DRLD t DAD t DRAK t t SAK DAAK Figure 10. Memory Read –19– ADSP-21020 t HDA t HDRH t RWR t HAK ...
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... ADSP-21020 Memory Write Parameter Timing Requirement: t xACK Delay from Address, Select DAAK t xACK Delay from xWR Low DWAK t xACK Setup before CLKIN High SAK t xACK Hold after CLKIN High HAK Switching Characteristic: t Address, Select to xWR Deasserted DAWH t Address, Select to xWR Low ...
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... CLKIN ADDRESS, SELECT DMPAGE, PMPAGE DMWR, PMWR t DCKWL DATA DMACK, PMACK DMRD, PMRD REV DAP t DAWH t t DAWL WW t WDE t DWAK t t DAAK SAK Figure 11. Memory Write –21– ADSP-21020 t DWHA t WWR t t HDWH DDWH t DDWR t HAK ...
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... System Inputs = PMD47-0, PMACK, PMTS, DMD39-0, DMACK, DMTS, CLKIN, IRQ3 0, RESET, FLAG3-0, BR. System Outputs = PMA23-0, PMS1-0, PMRD, PMWR, PMD47-0, PMPAGE, DMA31-0, DMS1-0, DMRD, DMWR, DMD39-0, DMPAGE, FLAG3-0, BG, TIMEXP. See the IEEE 1149.1 Test Access Port chapter of the ADSP-21020 User’s Manual for further detail. K/B/T Grade K/B/T Grade B/T Grade 20 MHz ...
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... TCK t STAP TMS,TDI TDO t SSYS SYSTEM INPUTS SYSTEM OUTPUTS REV TCK t HTAP t DTDO t HSYS t DSYS Figure 12. IEEE 1149.1 Test Access Port –23– ADSP-21020 ...
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... To determine the data output hold time in a particular system, first calculate t using the above equation. Choose DECAY the difference between the ADSP-21020’s output voltage and the input threshold for the device requiring the hold time. A typical V will be 0 the total bus capacitance (per ...
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... Figure 14). For different loads, these timing parameters should be derated. See the Hardware Configuration chapter of the ADSP-21020 User’s Manual for further information on derating of timing specifications. Figures 16 and 17 show how the output rise time varies with capacitance ...
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... ADSP-21020 ENVIRONMENTAL CONDITIONS The ADSP-21020 is available in a Ceramic Pin Grid Array (CPGA). The package uses a cavity-down configuration which gives it favorable thermal characteristics. The top surface of the package contains a raised copper slug from which much of the die heat is dissipated. The slug provides a surface for mounting a heat sink (if required) ...
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... Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. The length of the traces between the EZ-ICE probe connector and the ADSP-21020 test access port pins should be less than 1 inch. Note that the EZ-ICE probe adds two TTL loads to the CKIN pin of the ADSP-21020. ...
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... DMWR DMACK CLKIN NC NC PMTS PMD45 TDI DMTS DMRD NC PMRD PMD47 PMD43 PMS0 TDO IGND RESET IGND IVDD PMD46 ADSP-21020 TOP VIEW (PINS DOWN) DMA23 DMA27 IGND DMS0 IVDD DMD36 DMD31 DMA28 DMA31 DMS1 NC DMD38 DMD35 DMD30 DMD39 DMD37 DMD33 DMD32 ...
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... NC DMS1 DMA31 DMD26 DMD32 DMD33 DMD37 DMD39 DMS3 DMPAGE DMD23 EGND DMD29 EVDD DMD34 EGND –29– ADSP-21020 EVDD TCK EGND TMS PMA20 PMA17 DMWR TRST PMS1 PMA23 PMA19 EGND DMTS TDI PMPAGE PMA22 PMA18 ...
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... ADSP-21020 PGA PIN LOCATION NAME G16 DMA0 G17 DMA1 F18 DMA2 F17 DMA3 F16 DMA4 F15 DMA5 E18 DMA6 E17 DMA7 E16 DMA8 D18 DMA9 E15 DMA10 D17 DMA11 D16 DMA12 C18 DMA13 C17 DMA14 D15 DMA15 B18 DMA16 B17 DMA17 ...
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... TYP b 0.050 TYP 1 1.844 1.876 46.84 1.700 TYP 43.18 TYP 1 0.100 TYP 0.172 0.188 4.37 3 0.020 TYP 1.125 1.147 28.56 1.065 1.186 27.05 –31– ADSP-21020 TOP VIEW MAX 2.59 1.52 0.46 TYP 1.27 TYP 47.64 2.54 TYP 4.77 0.500 TYP 29 ...
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... C to +85 C ADSP-21020BG-100 – +85 C ADSP-21020BG-120 – +85 C ADSP-21020TG-80 – +125 C ADSP-21020TG-100 – +125 C ADSP-21020TG-120 – +125 C ADSP-21020TG-80/883B – +125 C ADSP-21020TG-100/883B – +125 C ADSP-21020TG-120/883B – +125 Ceramic Pin Grid Array. ...