adsp-21160n Analog Devices, Inc., adsp-21160n Datasheet
adsp-21160n
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adsp-21160n Summary of contents
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... DATA REGISTER FILE (PEY) BARREL 16 40-BIT MULT SHIFTER ALU One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 Fax:781/326-8703 S DSP Microcomputer ADSP-21160N JTAG TEST AND EMULATION I/O PORT DATA ADDR DATA ADDR EXTERNAL PORT IOD IOA 64 18 ADDR BUS MUX MULTIPROCESSOR INTERFACE ...
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... Multiprocessing Support Provides: Glueless Connection for Scalable DSP Multiprocessing Architecture Distributed On-Chip Bus Arbitration for Parallel Bus Connect Six ADSP-21160Ns Plus Host Six Link Ports for Point-to-Point Connectivity and Array Multiprocessing Serial Ports Provide: Two 50M Bits/s Synchronous Serial Ports with ...
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... Memory Write—Bus Master . . . . . . . . . . . . . . . . 22 Synchronous Read/Write—Bus Master . . . . . . . . 23 Synchronous Read/Write—Bus Slave . . . . . . . . . 25 Multiprocessor Bus Request and Host Bus Request . . . . . . . . . . . . . . . . . . . . . . 26 Asynchronous Read/Write—Host to ADSP-21160N . . . . . . . . . . . . . . . . . . . . . . 28 Three-State Timing—Bus Master, Bus Slave . . . . 30 DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 32 Link Ports —Receive, Transmit . . . . . . . . . . . . . . 34 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 JTAG Test Access Port and Emulation . . . . . . . . 39 Output Drive Currents ...
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... ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21160N has instruction cycle time. With its SIMD computational hardware running at 100 MHz, the ADSP-21160N can perform 600 million math operations per second ...
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... I/O proces- sor single cycle. On the ADSP-21160N, the memory can be configured as a maximum of 128K words of 32-bit data, 256K words of 16-bit data, 85K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to four megabits ...
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... ADSP- 21160N’s internal memory. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems con- taining up to six ADSP-21160Ns and a host processor. Master processor changeover incurs only one cycle of overhead. Bus 0xFFFF FFFF arbitration is selectable as either fixed or rotating priority ...
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... Maximum throughput for interprocessor data transfer is 400M bytes/s over the external port. Broadcast writes allow simultaneous transmission of data to all ADSP-21160Ns and can be used to implement reflective semaphores. CLKIN RESET RPBA 3 ID2–0 011 CLKIN RESET RPBA 3 ID2–0 010 CLKIN RESET ...
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... Vector interrupt support provides efficient execution of host commands. Program Booting The internal memory of the ADSP-21160N can be booted at system power-up from an 8-bit EPROM, a host processor, or through one of the link ports. Selection of the boot source is controlled by the BMS (Boot Memory Select), EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins ...
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... This document is updated regularly to keep pace with improvements to emulator support. Additional Information This data sheet provides a general overview of the ADSP-21160N architecture and functionality. For detailed information on the ADSP-2116x family core architecture and instruction set, refer to the ADSP-21160 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference ...
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... In synchronous access modes, the MS3–0 outputs assert with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. MS3–0 has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x. RDL Memory Read Low Strobe ...
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... It is asserted for every cycle after that, except for the last data request cycle (denoted by RDx or WRx asserted and BRST negated). A keeper latch on the DSP’s BRST pin maintains the input at the level it was last driven (only enabled on the ADSP-21160N with ID2–0 = 00x). ...
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... Priority Access. Asserting its PA pin allows an ADSP-21160N bus slave to interrupt I/O/T background DMA transfers and gain access to the external bus connected to all ADSP-21160Ns in the system. If access priority is not required in a system, the PA pin should be left unconnected. PA has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x. ...
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... O/T Core Instruction Fetch. Signal is active low when an external instruction fetch is performed. Driven by bus master only. Three-state when host is bus master. CIF has internal pull-up resistor that is enabled on the ADSP-21160N with ID2–0 = 00x Core Power Supply. Nominally 1 and supplies the DSP’s core processor DDINT (40 pins) ...
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... ADSP-21160N SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Internal (Core) Supply Voltage DDINT AV Analog (PLL) Supply Voltage DD V External (I/O) Supply Voltage DDEXT T Case Operating Temperature CASE V High Level Input Voltage, IH1 V High Level Input Voltage, IH2 V Low Level Input Voltage, IL Specifications subject to change without notice. ...
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... composite average based on a range of low activity code. For more information, see Power Dissipation DD-INLOW 18 Idle denotes ADSP-21160N state during execution of IDLE instruction. For more information, see Power Dissipation 19 Applies to all signal pins. 20 Guaranteed, but not tested. ABSOLUTE MAXIMUM RATINGS ...
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... Figure 7). The bootstrap Schottky diode connected between the 1.9 V and 3.3 V power supplies protects the ADSP-21160N from partially powering the 3.3 V supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode protection circuitry. With this technique, if the 1 ...
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... If setup time is not met, one additional CLKIN cycle may SRST t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power-up Sequencing 3.3V I/O VOLTAGE REGULATOR 1.9V CORE VOLTAGE REGULATOR Figure 7. Dual Voltage Schottky Diode –17– ADSP-21160N Min Max 0 – 50 +200 0 200 4096t CK t CORERST ...
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... CLKIN (not including start-up time of external clock oscillator Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset. ...
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... For Timer, see Table 8 and Figure 11. Table 8. Timer Parameter Switching Characteristic t CLKIN High to TIMEXP DTEX CLKIN t DTEX TIMEXP REV SIR t IPW Figure 10. Interrupts Figure 11. Timer –19– ADSP-21160N Min Max Unit 2 HIR Min Max Unit DTEX ...
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... ADSP-21160N Flags For Flags, see Table 9 and Figure 12. Table 9. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI FLAG3–0 IN Delay After RDx/WRx Low t DWRFI FLAG3–0 IN Hold After RDx/WRx Deasserted t HFIWR ...
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... RDx DATA ACK CLKIN WRx DMAGx REV. 0 apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. Min ...
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... WD E DATA t DAA K ACK CLKIN RDx DMAGx apply when the ADSP-21160N is the bus master accessing external memory space in asynchronous access mode. Note that timing for ACK, DATA, RDx, WRx, and DMAGx strobe timing parameters only applies to asynchronous access mode. Min ...
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... Figure 15. Use these specifications for inter- facing to external memory systems that require CLKIN—relative timing or for accessing a slave ADSP-21160N (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read–Bus Master Table 12. Synchronous Read/Write— ...
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... ADSP-21160N CLKIN t DCKOO CLKOUT t DADDO ADDRESS MSx, BRST, CIF PAGE ACK (IN) ACK (OUT) READ CYCLE RDx DATA (IN) WRITE CYCLE WRx DATA (OUT) Figure 15. Synchronous Read/Write—Bus Master t CKOP t t CKWH t DPGO t SACKC t t DACKMO ACKMTR t DRWL t DRWL t DDATO –24– CKWL ...
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... ACK Hold After CLKIN HACKO CLKIN ADDRESS t DACKC ACK READ ACCESS RDx DATA (OUT) WRITE ACCESS WRx DATA (IN) REV SADDI t DDATO t Figure 16. Synchronous Read/Write—Bus Slave –25– ADSP-21160N Min Max 5 CCLK 1.5 10 1.5 t HADDI t HACKO t t SRWI HRWI ...
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... Multiprocessor Bus Request and Host Bus Request See Table 14 and Figure 17. Use these specifications for passing of bus mastership between multiprocessing ADSP-21160Ns (BRx host processor, both synchronous and asynchronous (HBR, HBG). Table 14. Multiprocessor Bus Request and Host Bus Request Parameter Timing Requirements ...
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... O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 17. Multiprocessor Bus Request and Host Bus Request REV HHBRI t DHBGO t HHBGO t DBRO t HBRO t DPASO t DPAMO t SRP BAI t HRPBAI t T RDY HG t HBGRCSV –27– ADSP-21160N t TRP AS t PATR t S HBG I t HHBG I t SBRI t HBRI t ARDY TR ...
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... REDY (O/D) or (A/D) Low Delay After WRx/CS Low t DRDYWRL t REDY (O/D) or (A/D) Low Pulsewidth for Write RDYPWR After HBG is returned by the ADSP-21160N, the host can drive the RDx and WRx pins to access the ADSP-21160N’s internal 16, Figure 18, and memory or IOP registers. HBR and HBG are assumed low for this timing. – ...
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... READ CYCLE ADDRESS/ CS RDx D ATA (OUT) REDY (O/ D) REDY (A/D) Figure 18. Asynchronous Read—Host to ADSP-21160N WRITE CYCLE ADDRESS CS WRx DATA (I N) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN ACTIVE DRIVE Figure 19. Asynchronous Write—Host to ADSP-21160N REV YRD L ...
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... ADSP-21160N Three-State Timing—Bus Master, Bus Slave See Table 17 and Figure 20. These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host tran- sition cycles (HTC) as well as the SBTS pin. Table 17. Three-State Timing— ...
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... MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RDx, WRx, MSx, PAGE, DMAGx. BMS (IN EPROM BOOT MODE) Figure 20. Three-State Timing—Bus Master, Bus Slave REV STSCK t HTSCK t t MIENHG MITRA, MITRS, t DATTR t ACKTR t CDCTR t MENHBG –31– ADSP-21160N t MITRHG t ATRHBG t STRHBG t PTRHBG t BTRHBG ...
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... ADSP-21160N DMA Handshake See Table 18 and Figure 21. These specifications describe the three DMA handshake modes. In all three modes, DMARx is used to initiate transfers. For handshake mode, DMAGx controls the latching or enabling of data externally. For external hand- shake mode, the data transfer is controlled by the ADDR31–0, RDx, WRx, PAGE, MS3– ...
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... TIMING SPECIFICATIONS FOR ADDR31–0, RDx, WRx, MS3–0 AND ACK ALSO APPLY HERE. REV DMARLL t SDRC t WDR t DDGL t W DGL t DATDRH t SDATDG DGW RL DGW RH t DGRDL t DRDGH t DADGH Figure 21. DMA Handshake –33– ADSP-21160N t DMARH t HDGC t W DGH t DATRDGH t VDATDGH t HDATIDG t DGW RDR t DDGHA ...
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... ADSP-21160N Link Ports —Receive, Transmit For Link Ports, see Table 19, Table 20, Figure 23. Calculation of link receiver data setup and hold, relative to link clock, is required to determine the maximum allowable skew that can be introduced in the transmission path, between LDATA and LCLK. Setup skew is the maximum delay ...
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... DLDCH t HLDCH LDAT(7:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH REV. 0 LAST NIBBLE/BYTE FIRST NIBBLE/BYTE TRANSMITTED TRANSMITTED t t SLACH HLACH Figure 23. Link Ports—Transmit –35– ADSP-21160N LCLK INACTIVE (HIGH) t DLACLK ...
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... ADSP-21160N Serial Ports For Serial Ports, see Table 21, Table 22, Table 25, Table 26, Table 27, Figure 24, and determine whether communication is possible between two Table 21. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK ...
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... DDTE HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT 2ND BIT t DDTLFSE –37– ADSP-21160N Min Max 4.5 –1.5 7.5 0 0.5t –1.5 0.5t +1.5 SCLK SCLK Min Max 13 1.0 2ND BIT Unit Unit ns ns ...
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... ADSP-21160N DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t t SFSI HOFSE RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT— INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSI ...
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... TDO SYSTEM INPUTS SYSTEM OUTPUTS Figure 26. JTAG Test Access Port and Emulation REV. 0 Table 28 and TCK t t STAP HTAP t DTDO t t DSYS –39– ADSP-21160N Min Max SSYS HSYS Unit ...
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... ADSP-21160N Output Drive Currents Figure 27 shows typical I–V characteristics for the output drivers of the ADSP-21160N. The curves represent the current drive capability of the output drivers as a function of output voltage 3.47V, –45°C DDEXT V = 3.3V, 25°C 60 DDEXT 3.11V, 115°C ...
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... To determine the data output hold time in a particular system, first calculate t using the equation given above. Choose V DECAY to be the difference between the ADSP-21160N’s output voltage and the input threshold for the device requiring the hold time. A typical V will be 0 the total bus capacitance (per data ...
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... Metric PBGA (Plastic Ball Grid Array) package. Thermal Characteristics 200 250 The ADSP-21160N is specified for a case temperature (T To ensure that the T a heatsink and/or an air flow source may be used. Use the cen- terblock of ground pins (PBGA balls: F7-14, G7-14, H7-14, J7-14, K7-14, L7-14, M-14, N7-14, P7-14, R7-15) to provide thermal pathways to the printed circuit board’ ...
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... F20 L2CLK G20 CLKIN L01 K02 CLK_CFG_1 L02 K03 AGND L03 K04 CLK_CFG_2 L04 K05 V L05 DDEXT K06 V L06 DDINT –43– ADSP-21160N Pin Name Pin No. DATA[28] D01 DATA[25] D02 DATA[20] D03 DATA[19] D04 DATA[12] D05 V D06 DDEXT V D07 DDINT V D08 ...
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... ADSP-21160N Table 32. 400-Ball Metric PBGA Pin Assignments (continued) Pin Name Pin No. Pin Name GND J07 GND GND J08 GND GND J09 GND GND J10 GND GND J11 GND GND J12 GND GND J13 GND GND J14 GND V J15 V DDINT DDINT V J16 ...
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... Pin No. V18 L5DAT[1] W18 V19 L5DAT[3] W19 V20 L5DAT[5] W20 GND AV DD AGND I/O SIGNALS –45– ADSP-21160N Pin Name Pin No. DMAR1 Y18 EBOOT Y19 L5CLK Y20 ...
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... ADSP-21160N The ADSP-21160N comes Metric PBGA package with 20 rows of balls. 27.20 27.00 26.80 TOP VIEW 2.49 2.32 2.15 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-034-BAL-2. 2. CENTER FIGURES ARE NOMINAL DIMENSIONS. 3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. ...
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