MC74HCT273ADWG ON Semiconductor, MC74HCT273ADWG Datasheet - Page 5

• Manufacturer Part Number: MC74HCT273ADWG
• Description: IC FLIP FLOP OCTAL D 20-SOIC
• Manufacturer: ON Semiconductor
• Series: 74HCTr
• Type: D-Type Busr

Specifications of MC74HCT273ADWG

• Function: Reset
• Output Type: Non-Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 30MHz
• Delay Time - Propagation: 25ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: HCT
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Package Type: SOIC W
• Propagation Delay Time: 35ns
• Low Level Output Current: 4mA
• High Level Output Current: -4mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Number Of Circuits: 8
• Logic Type: D-Type Flip-Flop
• Input Type: Single-Ended
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HCT273ADWG; MC74HCT273ADWGOS

CLOCK
CLOCK
DATA
Q
10%
1.3 V
90%
0.3 V
1.3 V
2.7 V
1.3 V
t
r
t
w
t
t
su
PLH
Figure 1.
Figure 3.
t
TLH
1/f
VALID
max
1.3 V
t
t
f
PHL
t
h
t
THL
INPUTS
DATA
CLOCK
RESET
3.0 V
GND
3.0 V
GND
3.0 V
GND
D0
D1
D2
D3
D4
D5
D6
D7
EXPANDED LOGIC DIAGRAM
SWITCHING WAVEFORMS
3
4
7
8
13
14
17
18
11
1
http://onsemi.com
RESET
CLOCK
5
Q
D R
D R
D R
D R
D R
D R
D R
D R
C
C
C
C
C
C
C
C
Q
Q
Q
Q
Q
Q
Q
Q
*Includes all probe and jig capacitance
1.3 V
t
2
5
6
9
12
15
16
19
w
1.3 V
DEVICE
UNDER
t
PHL
TEST
Figure 4. Test Circuit
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
Figure 2.
OUTPUT
t
rec
TEST POINT
1.3 V
C
L
*
3.0 V
GND
3.0 V
GND