z8934050fsc ZiLOG Semiconductor, z8934050fsc Datasheet
z8934050fsc
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z8934050fsc Summary of contents
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FEATURES Part Number Speed Z89340 50 MHz 64 High-Speed Audio Processing Units (APUs) or 128 Half-Speed APUs 3-D Sound Capability Downloadable Sample Capability 8-Channel, 20-Bit Linear PCM Audio Generator Output Sampling Rates kHz Supports 16-, 18-, and ...
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Z89340 Digital Wavetable Engine GENERAL DESCRIPTION (Continued) ISA Interface Sound Blaster Registers FM Emulation Figure 1. Z89340 Simplified Functional Block Diagram 1-2 Synchronous Dual Port Audio Control Processor RAM Unit MIDI IDE (MPU 401) CD-ROM Port Interface ...
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PIN IDENTIFICATION 120 GND MIDI_TX CODEC_SCLK_0 CODEC_SD_IN_0 CODEC_SD_OUT_0 CODEC_STROBE_0 CODEC_STROBE_1 CODEC_STROBE_2 CODEC_STROBE_3 VCC CLOCK GND MODE_0 MODE_1 MODE_2 MODE_3 AUX_CS0 AUX_CS1 AUX_CS2 AUX_CS3 VCC GND RAS CAS DRAM_OE DRAM_WE ROMADD21 ROMADD22 ROMADD23 ROMADD20 ROMADD18 ROMADD19 ROMADD17 ROMADD08 ROMADD07 ROMADD09 ROMADD06 ...
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Z89340 Digital Wavetable Engine PIN IDENTIFICATION (Continued) Pin # Symbol 1 GND 2 ROMADD11 3 ROMADD04 4 ROMADD12 5 ROMADD03 6 ROMADD13 7 ROMADD02 8 ROMADD14 9 ROMADD01 10 ROMADD15 11 ROMADD00 12 ROMADD16 13 WAVE_DATA_OE 14 WAVE_DATA_WRITE 15 WAVE_DATA_15 ...
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Pin # Symbol 60 ISA_IRQ_11 61 ISA_IRQ_10 62 ISA_IOCS16 63 Reserved 64 ISA_IRQ_05 65 ISA_IRQ_07 66 CLKOUT 67 ISA_DRQ_01 68 ISA_DACK_01 69 ISA_DRQ_03 70 ISA_DACK_03 71 ISA_IOR 72 ISA_IOW 73 ISA_IRQ_09 74 ISA_RESDRV 75–79 ISA_SA00–SA04 GND ...
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Z89340 Digital Wavetable Engine PIN IDENTIFICATION (Continued) Pin # Symbol 144 CAS 145 DRAM_OE 146 DRAM_WE 147–149 ROMADD21–23 150 ROMADD20 151–153 ROMADD18,19, 17 154 ROMADD08 155 ROMADD07 156 ROMADD09 157 ROMADD06 158 ROMADD10 159 ROMADD05 160 V CC 1-6 Table ...
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ABSOLUTE MAXIMUM RATINGS Sym Description V Supply Voltage CC T Storage Temp STG – Voltage on any Pin I Maximum Output Leakage OL per I/O Pin T Oper Ambient Temp. A Stresses greater than those listed under Absolute Maxi- mum ...
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Z89340 Digital Wavetable Engine AC CHARACTERISTICS DMA Write/Playback Timing No. Description 1 DRQ Low from /DACK Low 2 /DACK High to DRQ High 3 Write Enable Width 4 /DACK Hold from End of /IOW 5 Data Setup to End of ...
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DMA Read/Record Timing Diagram No. Description 1 DRQ Low from /DACK Low 2 /DACK High to DRQ High 3 /DACK Hold Time from End of /IOR 4 Data Access Time from Read Enable 5 Data Hold Time from End of ...
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Z89340 Digital Wavetable Engine AC CHARACTERISTICS (Continued) External ROM Reading Timing Diagram CLK ROMADD00–23 RAS/ CAS WOE (CAS Case Only) Figure 5. Sample Memory Address Timing Diagram Figure 6. Sample Memory Read Timing Diagram 1- ...
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MIDI Timing Diagrams SCLK Start MIDI_TX Bit SCLK Start MIDI_RX Bit DS96DSP0201 . . . . . . MSB 8 Bits Figure 7. MIDI Transmit Timing Diagram . . . . . . MSB 8 Bits Figure 8. MIDI Receive ...
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Z89340 Digital Wavetable Engine CODEC INTERFACE TIMING DIAGRAM CODEC_STROBE_n CODEC_SCLK_n CODEC_SDIN_n CODEC_SDOUT_n PIN FUNCTIONS ADC_VREF_HI, ADC_VREF_LO. Analog-to-Digital Con- verter Voltage Reference. ADC_0–3 (I/O). Joystick button 0-3. ADC_4–7 (Input). Game port 4-7. AGND. Analog Ground. AUX_CS0–3 (Ouput). Auxiliary chip-select. These pins ...
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Z89340 Digital Wavetable Engine PIN FUNCTIONS (Continued) ISA_MEMW (I/O). ISA Memory Write. ISA_SA_0–4 (I/O). ISA Address Bus. ISA_SD_08–15 (I/O). Data Bus. This data bus is used to transfer data between PC and the Z89340. The lines map directly to the ...
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Z89340 Digital Wavetable Engine FUNCTIONAL DESCRIPTION Digital Audio Input and Output The Z89340 has eight output registers with signals that can be sent to a DAC or CODEC. Four of these can be used for quadraphonic output and have a ...
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Wavetable Synthesis Another method of synthesizing sound is sometimes called wavetable synthesis. The Wavetable Mode Oscilla- tor has some wavetable-synthesis extensions that set it apart from the Sample Loop Oscillator. With wavetable synthesis, one or more complete periods of a ...
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Z89340 Digital Wavetable Engine FUNCTIONAL DESCRIPTION (Continued) Figure 10. General-Purpose Oscillator Address Map 1- DS96DSP0201 ...
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ADPCM Oscillator The ADPCM Oscillator works in much the same way as the Sample Loop and Wavetable Oscillators. The main differ- ences are that, due to the nature of ADPCM, the frequency cannot be negative (you cannot with the Sample ...
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Z89340 Digital Wavetable Engine FUNCTIONAL DESCRIPTION (Continued) Tape Loop Oscillator The Tape Loop Oscillator takes its input from an input reg- ister, an effects channel submix register. It then reads a sample from wave RAM, and writes the ...
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Dual Tap-Reader As part of the reverb algorithm, the Dual Tap-Reader Os- cillator can pick additional taps in the Tape Loop delay line. The samples gathered are then scaled, summed, filtered, and sent to a submix register or one or ...
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Z89340 Digital Wavetable Engine FUNCTIONAL DESCRIPTION (Continued) Input Mixer The Input Mixer reads input from two sources (input regis- ters, submix registers or effects channels), scales the two samples, sums, filters, and sends the output to the desired 1-20 channel(s). ...
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Input Data Streamer Samples can be moved via DMA from the CPU host RAM to the Z89340 wavetable RAM space channels Figure 15. The Input Data Streamer Address Map OSCILLATOR PARAMETER BLOCKS An oscillator is controlled by ...
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Z89340 Digital Wavetable Engine OSCILLATOR PARAMETER BLOCKS (Continued) Frequency Low address 1 Envelope-type ATFP bits 0 and 1 Four types of envelope segments are supported, but only one at a time. Amplitude/Tremolo/Filter/Pan Envelope- type control bits. 00-Amplitude 01-Tremolo 10-Filter 11-Pan. ...
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Wave Endpoint Lo/ AWS/Interleave Size address 8 ATFP Flags bits 0 and 1 These bits are active for the selected envelope types in Frequency Lo. The bits have a separate meaning for Tremolo from the other types. Amplitude/Filter/Pan envelope flag ...
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Z89340 Digital Wavetable Engine OSCILLATOR PARAMETER BLOCKS (Continued) Effects Send Control address C Effects Attenuation(s) These six bits control the amount of signal that will be sent to the selected Effects Channel (bits 6-7). Since the signal will be sent ...
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FRONT channels left to right. 20-2f stereo pan REAR channels left to right. 3d sent to one of 32 submix registers. The submix register is chosen with low five bits of the Effects Send Control. Submix registers ...
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Z89340 Digital Wavetable Engine OSCILLATOR PARAMETER BLOCKS (Continued) Frequency Hi address 3 Frequency Hi These are: Extended Opcode With the Tape Loop Oscillator, the upper four bits of Fre- quency Hi are one of the extended opcodes and must be ...
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ROM2-ROM7 (Wavetable Mode Oscillator only) For Wavetable Mode Oscillators this should be 0. ROM0-ROM7 (Sample Loop Oscillator only) A sample sequence is played by setting Wave Pointer to the first sample in the sequence and Wave Endpoint to the last ...
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Z89340 Digital Wavetable Engine OSCILLATOR PARAMETER BLOCKS (Continued) Polar Pan Control address 10 Polar Pan Angle There are four main output channels. The spatial location among them is specified with a modified polar coordi- nate—a value ...
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PACKAGE INFORMATION DS96DSP0201 160-Pin QFP Package Diagram Z89340 Digital Wavetable Engine 1 1-29 ...
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... Z89340 Digital Wavetable Engine ORDERING INFORMATION Z89340 50 MHz 160-Pin QFP Z8934050FSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. Package F = Quad Flat Pack (QFP) Temperature +70 C Speed MHz Environmental C = Plastic Standard ...