z90102 ZiLOG Semiconductor, z90102 Datasheet

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z90102

Manufacturer Part Number
z90102
Description
40-pin Low-cost Digital Television Controller
Manufacturer
ZiLOG Semiconductor
Datasheet
FEATURES
8-Bit CMOS Microcontroller for Consumer
Television, Cable and Satellite Receiver Ap-
plications.
Device
Z90102
Z90103
Z90104
Note: *General-Purpose
GENERAL DESCRIPTION
The Z90102/3/4 40-pin Low-Cost Digital Television Con-
troller are members of the Z8
chip family with 4, 6, and 8 KB of ROM and 236 bytes of
RAM. The device is offered in a 40-pin package and is
DS97TEL1902
Lowest Cost DTC Family Member
Low Power Consumption
Fast Instruction Pointer - 1.5 m s @ 4 MHz
Two Standby Modes - STOP and HALT
Low Voltage Detection/Voltage Sensitive Reset
Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input,
3-Bit Output) Register Mapped Ports
Port 6 (6-Bit Input and Tristate Comparator AFC Input)
Memory Mapped I/O Ports
All Digital CMOS Levels Schmitt-Triggered
Two Programmable 8-Bit Counter/Timers each with 6-
Bit Programmable Prescaler.
Six Vectored, Priority Interrupts from Six Different
Sources
ROM
(KB)
4
6
8
®
(Bytes)
STOP Mode MCU single-
RAM*
236
236
236
I/O
24
24
24
Z90102/103/104
40-P
T
CMOS compatible. The DTC offers mask programmed
ROM which enables the Z8
ume production application device embedded with a cus-
tom program (customer supplied program) and combines
ELEVISION
Clock Speed up to 4 MHz
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC or External Clock Drive
Permanently Enabled
Watch-Dog/Power-On Reset Timer
3K x 6-Bit Character Generator ROM
120 x 7-Bit Video RAM
Mask Programmable 96-Character Set Display. The
90102 and 90103 6-Row x 20 Column Format, 12x15
Pixel Character Cell. The 90104 8-Row x 20 Column
Format 12x15 Pixel Character Cell. The 90102, 90103
90104 Capable of supporting English, Korean, Thai,
Chinese and Japanese High Resolution Characters.
Fully Programmable Color Attributes Including Row
Character,
Background/Position, Bar Graph Color Change, and
Character Size.
Programmable Display Position and Character Size
Control
One Pulse Width Modulator (14-Bit Resolution) for
Voltage Synthesis Tuner Control.
Three Pulse Width Modulator (8-Bit Resolution) for
Picture Control
Three Pulse Width Modulators (6-Bit Resolution) for
Audio Control
IN
L
OW
-C
C
Row
ONTROLLER
OST
P
RODUCT
®
Background/Fringes,
D
MCU to be used in a high vol-
IGITAL
S
PECIFICATION
Frame
1
1
1

Related parts for z90102

z90102 Summary of contents

Page 1

... Two Programmable 8-Bit Counter/Timers each with 6- Bit Programmable Prescaler. Six Vectored, Priority Interrupts from Six Different Sources GENERAL DESCRIPTION The Z90102/3/4 40-pin Low-Cost Digital Television Con- ® troller are members of the Z8 STOP Mode MCU single- chip family with 4, 6, and ROM and 236 bytes of RAM ...

Page 2

... PWM ports used to vary picture levels. 2 For DTC applications demanding powerful I/O capabili- ties, the Z90102/3/4 fulfills this with 24 I/O pins dedicated to input and output. These lines are grouped into three ports, and are configurable under software control to pro- vide timing, status signals, parallel I/O and an address/da- ta bus for interfacing to external memory ...

Page 3

... KB Program ROM Z8 CPU Core 256 Byte Register File Port 0 Port 1 A8-15 AD0-7 120 Byte Character RAM 3 Kbyte Character ROM Figure 1. Functional Block Diagram Z90102/90103/90104 P27 P26 P25 Port 2 P24 P23 P22 P21 P20 PWM 1 PWM 1 14 -bit PWM 6 PWM 6 to ...

Page 4

... IN 20 OSC OUT 21 HSYNC 22 VSYNC 23 Vred 4 PWM1 1 21 P35 P36 P34 P31 P30 XTAL1 Z90102 XTAL2 Z90103 /RESET Z90104 P60 40-Pin DIP GND P61 P62 VCC P63 P64 P65 AFCIN OSCIN 20 40 OSCOUT Figure 2. 40-Pin Mask-ROM Plastic DIP Table 1. 40-Pin Mask-ROM Plastic DIP ...

Page 5

... Table 1. 40-Pin Mask-ROM Plastic DIP Function Video Green Video Blue Video Blank Port 2, Pins 0,1,2,3,4,5,6,7 Pulse Width Modulator 11 Pulse Width Modulator 10 Pulse Width Modulator 9 Pulse Width Modulator 8 Pulse Width Modulator 7 Pulse Width Modulator 6 Z90102/90103/90104 Direction 1 Output Output Output In/Output Output Output Output Output Output ...

Page 6

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller PIN DESCRIPTION XTAL1, XTAL2. (time-based input, output, respectively). These pins connect to the internal parallel-resonant clock crystal (4 MHz max) oscillator circuit with two capacitors to GND. XTAL1 is also used as an external clock input. SCLK System Clock. SCLK is the internal system clock. ...

Page 7

... Min Max –0.3 +7 –0.3 V +0.3 CC –0.3 V +0.3 CC –0.3 13.2 –10 –100 20 200 † –65 +150 From Output Under Test Figure 3. Test Load Diagram Z90102/90103/90104 Units Notes pin mA All total mA 1 pin mA All total C VDD RLL RLH 150 ...

Page 8

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller CAPACITANCE T = 25° GND = 0V; Freq =1.0 MHz; unmeasured pins to GND Parameter Max Input capacitance 10 Output 20 capacitance I/O capacitance 25 AFCIN input 10 capacitance DC CHARACTERISTICS T = 0°C to +70° +4.5V to +5.5V; FOSC = 4 MHz A CC Sym Parameter V Input Voltage Low IL V Input XTAL/Osc In Low ...

Page 9

... Zilog AC CHARACTERISTICS Timing Diagrams XTAL1 TIN IRQN DS97TEL1902 40-Pin Low-Cost Digital Television Controller Figure 4. External Clock Figure 5. Counter Timer 8 9 Figure 6. Interrupt Request Z90102/90103/90104 ...

Page 10

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller VCC Internal /RESET External /RESET HSYNC OSC2 Figure 7. Power-On Reset 13 Figure 8. On-Screen Display Zilog 11 14 DS97TEL1902 ...

Page 11

... WDT Refresh Time Notes: Refer to DC Characteristics for details on switching levels. DS97TEL1902 40-Pin Low-Cost Digital Television Controller = 4 MHz OSC Min Max 250 1000 15 125 70 3TpC 8TpC 100 70 3TpC 3TpC 25 100 200 5TpC 2TpV 3TpV 1TpV 12 Z90102/90103/90104 1 Unit ...

Page 12

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION The Z8 DTCincorporates special functions to enhance the Z8’s versatility in consumer, industrial and television con- trol applications. Pulse Width Modulator (PWM). The has seven PWM channels (Figure 9). There are three types of PWM cir- cuits: PWM1 (one channel of 14-bit resolution) typically ...

Page 13

... Zilog DS97TEL1902 Figure 10. On-Screen Display Block Diagram Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller 1 13 ...

Page 14

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION (Continued) The OSD features are as follows: Character Color: Seven kinds of color are specified on a row basis. Character Pixel Size: Four character pixel sizes are selected for a high resolution (1HL, 2HL, 3HL, and 4HL) Horizontal Line (HL) ...

Page 15

... FD11H FD51H FD71H FD32H FD12H FD52H FD72H FD33H FD13H FD53H FD73H FD14H FD34H FD54H FD74H LSB Figure 12. Video RAM Map (Write/Read Registers) Z90102/90103/90104 ROW5 ROW6 FD80H FDA0H FD81H FDA1H FD82H FDA2H FD83H FDA3H FD84H FDA4H FD85H FDA5H FD86H FDA6H FD87H FDA7H ...

Page 16

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION (Continued) Hex Address ...

Page 17

... PWM6 6-Bit Register (PWM6) PWM7 6-Bit Register (PWM7) PWM8 6-Bit Register (PWM8) PWM9 8-Bit Register (PWM9) PWM10 8-Bit Register (PWM10) PWM11 8-Bit Register (PWM11) Reserved Reserved Reserved Port 6 Input Port (PORT6) Figure 14. Program Memory Z90102/90103/90104 1 Hex Address FC00 FC01 FC02 FC03 FC04 FC05 FC06 ...

Page 18

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION (Continued) Memory Mapped Register. All control registers and I/O ports (except Port 2 and Port 3) are assigned to program memory space. Address space FC00H contains OSD con- trol registers, PWM output registers and Port 6 I/O regis- ters. Two bits of the decoded AFCIN port are assigned to Port 6 input port ...

Page 19

... Working Register Group Pointer Z8 Reg. File %FF %FO %7F %0F %00 Note: All General-Purpose registers, PWM Registers, and Video RAM registers, Port 4, 5, and 6 registers are undefined after reset. Figure 17. Z90102/3/4 Register File Reset Condition DS97TEL1902 Z8 STANDARD CONTROL REGISTERS REGISTER % Must be "0" ...

Page 20

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION (Continued) Stack. Either the internal register file or the external data memory is used for the stack. An 8-bit Stack Pointer is used for the internal stack that resides within the 236 gen- eral-purpose registers. Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit pro- grammable prescaler (PRE0 and PRE1) ...

Page 21

... Request DS97TEL1902 40-Pin Low-Cost Digital Television Controller two sources are claimed by Port 3 (P30, P31), one by VSYNC, two by the counter/timers, and one is software triggered only. IRQ IRQ IMR Global Interrupt IPR Enable Priority Logic Vector Select Figure 19. Interrupt Block Diagram Z90102/90103/90104 ...

Page 22

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller FUNCTIONAL DESCRIPTION (Continued) HALT Mode. The Z90102/3/4 is driven by two internal clocks, TCLK and SCLK. They both oscillate at the crystal frequency. TCLK provides the clock signal for the counter- timers and the interrupt block. SCLK provides the clock signal for all other CPU blocks ...

Page 23

... Zilog Watch-Dog Timer (WDT). The Z90102/3/4 is equipped with a permanently enabled Watch-Dog Timer which must be refreshed every 12 ms. Failure to refresh the timer re- sults in a reset of the device. The WDT is permanently en- abled and is initially reset upon POR. Every subsequent WDT instruction resets the timer. The Watch-Dog Timer may or may not be enabled during the STOP Mode ...

Page 24

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller STANDARD CHARACTER SETS 24 Zilog DS97TEL1902 ...

Page 25

... Low-Cost Digital Television Controller VCC OEN PAD OUT IN Figure 25. Input/Output Tristate VCC OD OEN PAD OUT IN Figure 26. Input/Output, Tristate, Open-Drain OEN PAD OUT Figure 27. Output Only, Tristate Z90102/90103/90104 VCC P PAD N 20 Ohm (Pad Type 4) VCC P PAD N 20 Ohm VCC P PAD N 25 ...

Page 26

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller SUMMARY (Continued) VCC N VCC OUT N Figure 28. Output Only, 12-Volt Open-Drain (Pad Type 7) VCC RESET N Figure 29. Reset Input Circuit (Pad Type 8) 26 PAD STOP N P67 N P66 Table 2. Mapping of Symbolic Pad Types to Pin RPU Pin Name XTAL1, OSCIN ...

Page 27

... Input/Output Port 0 Logic Level 0 1 Logic Level 1 F6H Input/Output Mode 0 Output Mode P6 1 Input Mode Z90102/90103/90104 03H P30 Input Port Stop-Mode Recovery Input P31 Input/T1 (input) P34 Output Port P35 Output Port P36 Output/T1, T0 (output) Reserved Figure 33. Port 3 Register ...

Page 28

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller DTC CONTROL REGISTER DIAGRAMS PWM Registers PWM1 UPPER FC12H Figure 35. PWM 1 High Value (Write Only) FC13H PWM1 LOWER Figure 36. PWM 1 Low Value (Write Only) FC18H PWM6 VAL Figure 37 ...

Page 29

... Only) DS97TEL1902 40-Pin Low-Cost Digital Television Controller PWM OUT Mode Control PWM 1 Output Port Reserved (Must be 0) Figure 44. PWM Port Output Register Z90102/90103/90104 FC11H Output Control 0 = Logic Level Logic Level 0 Reserved (Must be 0) (Write Only ...

Page 30

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller Z8 REGISTER DIAGRAMS FC00H OSDC CNTRL Figure 45. OSD Control Register (Write Only) FC01H VERT POS Figure 46. OSD Vertical Position Register (Write Only) FC02H HOR POS Figure 47 ...

Page 31

... External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out * Default After Reset Z90102/90103/90104 FD00H,FD20H,FD40H, FD60H,FD80H,FDA0H Row Background Color Red Green Blue Row Background On-Off 0 Off 1 On Character Color Red ...

Page 32

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller Z8 REGISTER DIAGRAMS (Continued) F4H R244 Figure 57. Counter/Timer 0 Register (F4H: Read/Write) F5H R245 PRE0 Default After Reset Figure 58. Prescaler 0 Register (F5H: Write Only) F6H R246 P2M Figure 59 ...

Page 33

... R255 SPL User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Z90102/90103/90104 FDH Reserved (Must be 0) Register Pointer Figure 65. Register Pointer (FDH: Read/Write) FEH 0 = Level Level 1 Figure 66. General-Purpose ...

Page 34

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller PACKAGE INFORMATION 34 Figure 68. 40-Pin DIP Package Diagram Zilog DS97TEL1902 ...

Page 35

... Zilog ORDERING INFORMATION Z90102, Z90103, Z90104 4 MHz 40-pin DIP Z90102/3/404PSC For fast results, contact your local Zilog sales office for as- sistance in ordering the part desired. CODE Package P = Plastic DIP Temperature S = 0°C to +70°C Example: Z 890103 DS97TEL1902 40-Pin Low-Cost Digital Television Controller ...

Page 36

... Z90102/90103/90104 40-Pin Low-Cost Digital Television Controller 36 Zilog DS97TEL1902 ...

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