at40k20al-1dqc ATMEL Corporation, at40k20al-1dqc Datasheet - Page 11

• Manufacturer Part Number: at40k20al-1dqc
• Description: At40k05al 5k - 50k Gates Coprocessor Fpga With Freeram
• Manufacturer: ATMEL Corporation

RAM
2818F–FPGA–07/06
32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit
Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed
over four sector rows (plane 2). A 5-bit Input Address Bus connects to five vertical
express buses in the same column. A 5-bit Output Address Bus connects to five vertical
express buses in the same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
AT40KAL Series FPGA
CLK
CLK
CLK
CLK
Ain
WEN
OEN
32 x 4 RAM
Din
CLK
Dout
Aout
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