at40k20al-1dqc ATMEL Corporation, at40k20al-1dqc Datasheet - Page 28

• Manufacturer Part Number: at40k20al-1dqc
• Description: At40k05al 5k - 50k Gates Coprocessor Fpga With Freeram
• Manufacturer: ATMEL Corporation

AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Notes:
28
Cell Function
Async RAM
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
Sync RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
1. CMOS buffer delays are measured from a V
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
AT40KAL Series FPGA
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WECYC
WEL
WEH
AWS
AWH
DS
DH
DD
AD
OZX
OXZ
CYC
CLKL
CLKH
WCS
WCH
ACS
ACH
DCS
DCH
CD
AD
OZX
OXZ
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
CC
CC
= 3.6V, temperature = 0°C
= 3.0V, temperature = 70°C
Path
cycle time
we
we
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
oe -> dout
cycle time
clk
clk
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
rd addr -> dout
oe -> dout
oe -> dout
IH
of 1/2 V
CC
at the pad to the internal V
12.0
12.0
5.0
5.0
5.3
0.0
5.0
0.0
8.7
6.3
2.9
3.5
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
5.8
6.3
2.9
3.5
-1
IH
at A. The input buffer load is constant.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Pulse width low
Pulse width high
rd addr = wr addr
Pulse width low
Pulse width high
rd addr = wr addr
2818F–FPGA–07/06