at40k-fft ATMEL Corporation, at40k-fft Datasheet
at40k-fft
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at40k-fft Summary of contents
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... RAM. The processor is then instructed to compute the FFT, overwriting the input data in the RAM with the results. Upon completion of the FFT, the results may be read out from the RAM via the output data port. AT40K FPGA IP Core AT40K-FFT Rev. 1132A–08/98 1 ...
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... Figure 2. Example FFT processor configuration 1. Real input Imag input Input Clock Figure 3. Example FFT processor configuration 2. AT40K-FFT 2 Address Address Counter Counter Data RAM Butterfly ...
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... AT40K FPGA. These problems can be overcome if the butterfly calcula- tion is performed over two clock cycles. This balances the ...
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... T Re(B’)=(Im(-A+B)xIm(W )+Re(-A+B Re(W ))/2=Re((A-B)xW ). The other is fed into a differencing circuit which subtracts the two results, divides by two and truncates the result to 12 bits with rounding, yielding, AT40K-FFT 4 Delay Delay ...
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... MatLab FFT function. Timing Analysis Timing analysis of the design indicated a maximum clock speed of 21.2 MHz when using the AT40K30 part. Investi- gations into the limiting data path revealed this to be the delay from the twiddle factor address counter output, through the asynchronous twiddle factor ROM to the butter- fly’ ...
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... For large transform lengths the use of an external dual ported memory should be considered, this may also pro- vide faster data transfer times by reducing on chip bus loadings. AT40K-FFT 6 System performance could potentially be improved by pro- viding suitable buffering to permit concurrent data process- ing and IO. Double buffering designs would most probably have to use external memory devices ...
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