AT40K ATMEL [ATMEL Corporation], AT40K Datasheet
AT40K
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AT40K Summary of contents
Page 1
... Reusable, Fully Deterministic Logic and RAM Functions • Intellectual Property Cores – Fir Filters, UARTs, PCI, FFT and Other System Level Functions • Easy Migration to Atmel Gate Arrays for High Volume Production • Supply Voltage 5V for AT40K, and 3.3V for AT40KLV ™ ® ® ™ , Mentor , OrCAD ...
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... I/O counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC to 352-ball Square BGA, and support 5V designs for AT40K and 3.3V designs for AT40KLV. The AT40K/AT40KLV is designed to quickly implement high-performance, large gate count designs through the use of synthesis and schematic-based tools used Sun platform. Atmel’ ...
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... Devices range in size from 5,000 to 50,000 usable gates in the family, and have 256 to 2,304 registers. Pin locations are consistent throughout the AT40K/AT40KLV series for easy design migration in the same package footprint. The AT40K/AT40KLV series FPGAs utilize a reliable 0.6µ single-poly, CMOS process and are 100% factory-tested. ...
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... RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM nous or asynchronous operation. Note: Figure 1. Symmetrical Array Surrounded by I/O (AT40K20) AT40K/AT40KLV Series FPGA 4 1. The right-most column can only be used as single-port RAM. = Repeater Row ...
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... Figure 2. Floor Plan (Representative Portion) Note: 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = Vertical Repeater RV = Horizontal Repeater RH = Core Cell RAM RAM RAM RAM RAM RAM ...
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... Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resources on the AT40K/AT40KLV are used as a dual-function resources. Table 2 shows which buses are used in a dual-function mode and which bus plane is used ...
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... Figure 3. Busing Plane (One of Five) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA = AT40K/AT40KLV Core Cell = Local/Local or Express/Express Turn Point = Row Repeater = Column Repeater Express Express Bus Bus Local Bus 7 ...
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... This allows bus signals to switch planes to achieve greater route ability five simultaneous local/local turns are possible. The AT40K/AT40KLV FPGA core cell is a highly configurable logic block based around two 3-input LUTs ( ROM), which can be combined to produce one 4-input LUT. ...
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... Z D CLOCK RESET/SET Diagonal Direct Connect or Bus Y = Orthogonal Direct Connect or Bus W = Bus Connection Z = Bus Connection FB = Internal Feedback 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA "1" Pass gates "1" OE ...
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... SUM Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40K/AT40KLV core cell or can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the SUM (Registered) sum output in this diagram is registered ...
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... RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to the vertical express buses in the same column. Figure 7. RAM Connections (One Ram Block) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA CLK CLK CLK CLK ...
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... RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the “ AT40K Configuration Series” application note at www.atmel.com). ...
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WE 2-to-4 Decoder Write Address Din(0) Din(1) Din(2) Din(3) Din Dout Ain Aout WEN OEN Din(4) Din(5) Din(6) Din(7) Din Dout Ain Aout WEN OEN Din Dout Din Dout Aout Ain Ain Aout WEN WEN OEN OEN Din Dout Din ...
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... Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40K/AT40KLV FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Glo- bal Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock loca- tions ...
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... Figure 10. Clocking (for One Column of Cells) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Express Bus (Plane 4; Half Length at Edge) Repeater } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux “1” Sector Clock Mux Global Clock Line (Buried) “ ...
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... Set/Reset Scheme The AT40K/AT40KLV family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources ...
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... Figure 11. Set/Reset (for One Column of Cells) (Plane 5; Half Length at Edge) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Repeater “1” “1” Express Bus “1” “1” Any User I/O can Drive Global Set/Reset Lone Each Cell has a Programmable Set or Reset Sector Set/Reset Mux ...
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... Z) by programming an I/O’s Source Selection mux. Of course, the output can be normal (0 or 1), as well. SOURCE SELECTION MUX The Source Selection mux selects the source for the output signal of an I/O, see Figure 12 on page 20. AT40K/AT40KLV Series FPGA 18 0896C–FPGA–04/02 ...
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... Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40K/AT40KLV FPGA with core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing net- works running along the edges of the array ...
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... Figure 12. West I/O (Mirrored for East I/O) AT40K/AT40KLV AT40K/AT40KLV Series FPGA 20 “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (a) Primary I/O “0” “1” “0” PULL-UP “1” PAD PULL-DOWN (b) Secondary I/O CELL CELL CELL CELL CELL 0896C–FPGA–04/02 ...
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... Figure 13. South I/O (Mirrored for North I/O) AT40K/AT40KLV 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA (a) Primary I/O (a) Secondary I/O 21 ...
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... Figure 14. Northwest Corner (Similar for NE/SE/SW Corners) AT40K/AT40KLV PULL-DOWN AT40K/AT40KLV Series FPGA 22 PAD VCC TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY “0” “1” “0” PULL-UP “1” PAD PAD GND VCC GND TTL/CMOS DRIVE SCHMITT TRI-STATE DELAY CELL CELL CELL 0896C–FPGA–04/02 ...
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... Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 250°C ESD (R = 1.5K 100 pF)................................. 2000V ZAP ZAP DC and AC Operating Range – 5V Operation AT40K Operating Temperature (Case) V Power Supply CC Input Voltage Level (TTL) Input Voltage Level (CMOS) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA *NOTICE: ...
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... DC Characteristics – 5V Operation Commercial/Industrial/Military AT40K Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level Tri-state Output I OZH Leakage Current Low-level Tri-state Output I OZL Leakage Current ...
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... AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Cell Function Parameter Core 2-input Gate t (Maximum) PD 3-input Gate t (Maximum) ...
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... AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t All input IO characteristics measured from All output IO characteristics are measured as the average of t ...
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... AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Clocks and Reset Input buffers are measured from a V Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. ...
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... AC Timing Characteristics – 5V Operation AT40K Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Cell Function Parameter Async RAM Write t (Minimum) WECYC Write t (Minimum) ...
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... FreeRAM Asynchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA WE t AWS 0 ADDR OXZ DS DATA WE t AWS 0 WR ADDR PREV. WR DATA RD ADDR = WR ADDR OLD RD DATA 0 RD ADDR OE t OZX DATA t WEL ...
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... FreeRAM Synchronous Timing Characteristics Single-port Write/Read Dual-port Write with Read Dual-port Read AT40K/AT40KLV Series FPGA 30 CLK t WCS WE t ACS 0 ADDR OE t OXZ t DCS DATA CLK t WCS WE t ACS 0 WR ADDR t DCS WR DATA RD ADDR = WR ADDR 1 RD DATA 0 RD ADDR OE t OZX DATA ...
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... Supply Voltage (V ) .........................................-0.5V to +7.0V CC Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 250°C ESD (R = 1.5K 100 pF)................................. 2000V ZAP ZAP DC and AC Operating Range – 3.3V Operation AT40KLV Operating Temperature (Case) V Power Supply CC Input Voltage Level (CMOS) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent dam- age to the device ...
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... DC Characteristics – 3.3V Operation Commercial/Industrial AT40KLV Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level Tri-state Output I OZH Leakage Current Low-level Tri-state Output I OZL Leakage Current ...
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... AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Cell Function Parameter Core 2-input Gate t (Maximum) PD 3-input Gate t (Maximum) ...
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... AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t All input IO characteristics measured from All output IO characteristics are measured as the average of t ...
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... AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Maximum delays are the average of t Clocks and Reset Input buffers are measured from a V Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. ...
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... AC Timing Characteristics – 3.3V Operation AT40KLV Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: V Minimum times based on best case: V Cell Function Parameter Async RAM Write t (Minimum) WECYC Write t (Minimum) WEL Write t (Minimum) WEH Write t (Minimum) ...
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... Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O ...
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... I/O19 I/O27 I/O35 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. AT40K/AT40KLV Series FPGA 38 AT40K40 84 100 100 384 I/O PLCC ...
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... Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. On-chip tri-state. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O ...
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... I/O68 I/O37 I/O53 I/O69 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 40 AT40K40 84 100 100 384 I/O PLCC PQFP ...
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... I/O66 I/O86 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O ...
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... I/O103 I/O104 GND I/O105 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 42 AT40K40 84 100 100 384 I/O PLCC PQFP ...
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... Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O PLCC ...
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... I/O103 I/O137 (D6) (D6) (D6) Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 44 AT40K40 84 100 100 384 I/O PLCC PQFP TQFP ...
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... I/O116 I/O156 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O ...
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... VCC I/O87 I/O129 I/O173 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. AT40K/AT40KLV Series FPGA 46 AT40K40 84 100 100 384 I/O PLCC PQFP ...
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... Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 384 I/O ...
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... I/O154 I/O204 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. AT40K/AT40KLV Series FPGA 48 AT40K40 84 100 100 384 I/O ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 ...
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... GND I/O241 Notes: 1. Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. AT40K/AT40KLV Series FPGA 50 AT40K40 84 100 100 384 I/O ...
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... Pads labeled GND or VCC are internally bonded to Ground or VCC planes within the package. They have no direct con- nection to any specific package pin. 2. This package has an inverted die. 3. Shared with TSTCLK. No Connect. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K40 AT40K40LV 84 100 100 ...
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... A2 A25 A26 H26 N1 AE1 AE26 AF19 AF22 Note SBGA packages, Power and Ground pins do not connect directly to die. They connect to Power and Ground planes inside the package. AT40K/AT40KLV Series FPGA 52 (1) VCC Pins B2 B25 K1 K26 Y4 AC8 AC14 AF17 GND Pins ...
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... Plastic Quad Flat Package (PQFP) 240Q1 240-lead, Plastic Quad Flat Package (PQFP) 304Q1 304-lead, Plastic Quad Flat Package (PQFP) 352C1 252-ball, Enhanced, Low-profile Square Ball Grid Array Package (SBGA) 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA AT40K10/AT40K10LV 114 ...
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... AT40K05/AT40K05LV Ordering Information Usable Gates Operating Voltage 5,000 - 10,000 5.0V 5,000 - 10,000 5.0V 5,000 - 10,000 3.3V 5,000 - 10,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. AT40K/AT40KLV Series FPGA 54 Speed Grade (ns) Ordering Code 2 AT40K05-2AJC AT40K05-2AQC AT40K05-2RQC AT40K05-2BQC AT40K05-2CQC AT40K05-2DQC 2 AT40K05-2AJI AT40K05-2AQI AT40K05-2RQI AT40K05-2BQI AT40K05-2CQI AT40K05-2DQI ...
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... AT40K10/AT40K10LV Ordering Information Usable Gates Operating Voltage 10,000 - 20,000 5.0V 10,000 - 20,000 5.0V 10,000 - 20,000 3.3V 10,000 - 20,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering Code 2 AT40K10-2AJC AT40K10-2AQC AT40K10-2RQC AT40K10-2BQC AT40K10-2CQC AT40K10-2DQC 2 AT40K10-2AJI AT40K10-2AQI AT40K10-2RQI ...
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... AT40K20/AT40K20LV Ordering Information Usable Gates Operating Voltage 20,000 - 30,000 5.0V 20,000 - 30,000 5.0V 20,000 - 30,000 3.3V 20,000 - 30,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com AT40K/AT40KLV Series FPGA 56 Speed Grade (ns) Ordering Code 2 AT40K20-2AJC AT40K20-2AQC AT40K20-2RQC AT40K20-2BQC AT40K20-2CQC AT40K20-2DQC AT40K20-2EQC 2 AT40K20-2AJI AT40K20-2AQI AT40K20-2RQI AT40K20-2BQI AT40K20-2CQI ...
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... AT40K40/AT40K40LV Ordering Information Usable Gates Operating Voltage 40,000 - 50,000 5.0V 40,000 - 50,000 5.0V 40,000 - 50,000 3.3V 40,000 - 50,000 3.3V Note: 1. For military parts, contact Atmel at fpga@atmel.com. 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA Speed Grade (ns) Ordering Code 2 AT40K40-2BQC AT40K40-2DQC AT40K40-2EQC AT40K40-2FQC AT40K40-2BGC 2 AT40K40-2BQI AT40K40-2DQI AT40K40-2EQI AT40K40-2FQI ...
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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R AT40K/AT40KLV Series FPGA 58 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER ...
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... These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip defined as the distance from the seating place to the lowest point on the package body. 2325 Orchard Parkway San Jose, CA 95131 R 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA E1 SYMBOL TITLE 100T1, 100-lead ( 1.0 mm Body), Thin Plastic Quad Flat Pack (TQFP) ...
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... Dambar cannot be located on the lower radius or the lead foot defined as the distance from the seating plane to the lowest point of the package body. 2325 Orchard Parkway San Jose, CA 95131 R AT40K/AT40KLV Series FPGA TITLE 100Q4, 100-lead Body, 3.2 Form Opt., ...
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... These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip defined as the distance from the seating place to the lowest point on the package body. 2325 Orchard Parkway San Jose, CA 95131 R 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA XX E1 SYMBOL TITLE 144L1, 144-lead ( 1.4 mm Body), Low Profile ...
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... Dambar cannot be located on the lower radius or the lead foot defined as the distance from the seating plane to the lowest point of the package body. 2325 Orchard Parkway San Jose, CA 95131 R AT40K/AT40KLV Series FPGA TITLE 160Q1, 160-lead Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) ...
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... Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 2325 Orchard Parkway San Jose, CA 95131 R 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA TITLE 208Q1, 208-lead ( Body, 2 ...
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... Dambar cannot be located on the lower radius or the foot. The minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 2325 Orchard Parkway San Jose, CA 95131 R AT40K/AT40KLV Series FPGA TITLE 240Q1, 240-lead Body, 2.6 Form Opt., ...
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... The minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. 2325 Orchard Parkway San Jose, CA 95131 R 0896C–FPGA–04/02 AT40K/AT40KLV Series FPGA b L1 TITLE 304Q1, 304-lead Body, 2.6 Form Opt., Plastic Quad Flat Pack (PQFP) ...
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... JEDEC variations are based on fully populated ball arrays. Arrays can be depopulated as desired by removing balls from the fully populated array. 2325 Orchard Parkway San Jose, CA 95131 R AT40K/AT40KLV Series FPGA b∅ e Bottom View ...
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Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem ...