ep20k1000e Altera Corporation, ep20k1000e Datasheet - Page 11
ep20k1000e
Manufacturer Part Number
ep20k1000e
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet
1.EP20K1000E.pdf
(117 pages)
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Altera Corporation
Figure 3. LAB Structure
LEs drive local
MegaLAB, row,
and column
interconnects.
MegaLAB Interconnect
To/From
Adjacent LAB,
ESB, or IOEs
Local Interconnect
Row
Interconnect
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within an LAB or
adjacent LABs, allowing the use of a fast local interconnect for high
performance.
APEX 20K devices use an interleaved LAB structure. This structure allows
each LE to drive two local interconnect areas. This feature minimizes use
of the MegaLAB and FastTrack interconnect, providing higher
performance and flexibility. Each LE can drive 29 other LEs through the
fast local interconnect.
The 10 LEs in the LAB are driven by
two local interconnect areas. These LEs
can drive two local interconnect areas.
Figure 3
APEX 20K Programmable Logic Device Family Data Sheet
shows the APEX 20K LAB.
Column
Interconnect
To/From
Adjacent LAB,
ESB, or IOEs
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