at94k40al ATMEL Corporation, at94k40al Datasheet - Page 92

• Manufacturer Part Number: at94k40al
• Description: At94kal Series Field Programmable System Level Integrated Circuit
• Manufacturer: ATMEL Corporation

92
AT94KAL Series FPSLIC
The 8-bit Timer/Counter0 can select the clock source from CK, prescaled CK, or an external pin.
The 8-bit Timer/Counter2 can select the clock source from CK, prescaled CK or external
TOSC1.
Both Timers/Counters can be stopped as described in section
– TCCR0” on page 92
The various status flags (overflow and compare match) are found in the Timer/Counter Interrupt
Flag Register (TIFR). Control signals are found in the Timer/Counter Control Register (TCCR0
and TCCR2). The interrupt enable/disable settings are found in the Timer/Counter Interrupt
Mask Register – TIMSK.
When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscilla-
tor frequency of the CPU. To assure proper sampling of the external clock, the minimum time
between two external clock transitions must be at least one internal CPU clock period. The
external clock signal is sampled on the rising edge of the internal CPU clock.
The 8-bit Timer/Counters feature both a high-resolution and a high-accuracy usage with the
lower prescaling opportunities. Similarly, the high prescaling opportunities make the
Timer/Counter0 useful for lower speed functions or exact-timing functions with infrequent
actions.
Timer/Counters 0 and 2 can also be used as 8-bit Pulse Width Modulators (PWM). In this mode,
the Timer/Counter and the output compare register serve as a glitch-free, stand-alone PWM with
centered pulses. See “Timer/Counter 0 and 2 in PWM Mode” on page 95 for a detailed descrip-
tion on this function.
Timer/Counter0 Control Register – TCCR0
Timer/Counter2 Control Register – TCCR2
• Bit 7 - FOC0/FOC2: Force Output Compare
Writing a logic 1 to this bit forces a change in the compare match output pin PE1
(Timer/Counter0) and PE3 (Timer/Counter2) according to the values already set in COMn1 and
COMn0. If the COMn1 and COMn0 bits are written in the same cycle as FOC0/FOC2, the new
settings will not take effect until next compare match or Forced Output Compare match occurs.
The Force Output Compare bit can be used to change the output pin without waiting for a com-
pare match in the timer. The automatic action programmed in COMn1 and COMn0 happens as if
a Compare Match had occurred, but no interrupt is generated and the Timer/Counters will not be
cleared even if CTC0/CTC2 is set. The FOC0/FOC2 bits will always be read as zero. The setting
of the FOC0/FOC2 bits has no effect in PWM mode.
Bit
$33 ($53)
Read/Write
Initial Value
Bit
$27 ($47)
Read/Write
Initial Value
7
FOC0
R/W
0
7
FOC2
R/W
0
and
6
PWM0
R/W
0
6
PWM2
R/W
0
“Timer/Counter2 Control Register – TCCR2” on page
5
COM01
R/W
0
5
COM21
R/W
0
4
COM00
R/W
0
4
COM20
R/W
0
CTC0
CTC2
3
R/W
0
3
R/W
0
2
CS02
R/W
0
2
CS22
R/W
0
“Timer/Counter0 Control Register
1
CS01
R/W
0
1
CS21
R/W
0
0
CS00
R/W
0
0
CS20
R/W
0
92.
1138I–FPSLI–1/08
TCCR0
TCCR2