atam862-8 ATMEL Corporation, atam862-8 Datasheet
atam862-8
Related parts for atam862-8
atam862-8 Summary of contents
Page 1
... About Seven External Components 1. Description The ATAM862 single package dual-chip circuit. It combines a UHF ASK/FSK transmitter with a 4-bit microcontroller. It supports highly integrated solutions in car access and tire pressure monitoring applications, as well as manifold applications in the industrial and consumer segment available for the transmitting frequency range of 868 MHz to 928 MHz with data rates kbaud Manchester coded ...
Page 2
... Pin Configuration Figure 2-1. Pinning SSO24 Table 2-1. Pin Description: RF Part Pin Symbol Function 1 XTAL Connection for crystal 2 VS Supply voltage 3 GND Ground 4 ENABLE Enable input ATAM862-8 2 XTAL 1 24 ANT1 ANT2 GND 3 22 PA_ENABLE ENABLE 4 21 CLK NRESET 5 20 BP60/T3O BP63/T3I 6 19 ...
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... INT1 external interrupt input T3O Timer 3 output T3I Timer 3 input 4-MHz crystal input or 32-kHz crystal input or external clock input or external trimming resistor input 4-MHz crystal output or 32-kHz crystal output or external clock input – ATAM862-8 Configuration VS 100 CLK 100 PA_ENABLE 50k 20 µA ...
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... C Operation for Tire Pressure Systems 5. Description The PLL transmitter block has been developed for the demands of RF low-cost transmission systems, at data rates kbaud. The transmitting frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK systems. ATAM862-8 4 4590G–4BMCU–06/07 ...
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... INT6 BP40 BP41 BP42 BP43 BP50 BP52 BP53 BP60 INT3 VMI T2O INT3 INT6 INT1 T3O INT1 SC T2I SD ATAM862-8 ENABLE XTO µC UTCM Timer 1 interval- and watchdog timer Timer 2 T2I 8/12-bit timer T2O with modulator SD SSI SC Serial interface Timer 3 T3O 8-bit ...
Page 6
... The PLL transmitter block is activated by ENABLE = H. PA_ENABLE must remain L for t then the CLK signal can be taken to clock the microcontroller and the output power can be mod- ulated by means of pin PA_ENABLE. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The ATAM862-8 is switched back to standby mode with ENABLE = L. 7.2 FSK Transmission The PLL transmitter block is activated by ENABLE = H ...
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... Stray1 XTAL Crystal equivalent circuit = 9.2 pF ±2 6.8 pF ±5%, a switch port with Stray1 = 3.2 pF ±10% and a crystal with C 0 Load,opt to deliver the DC current the 0.53 pF output capacitance of the power amplifier is || j/(2 f 0.53 pF) = (166 + j226) ATAM862-8 C Stray2 Switch = 3 pF ± ...
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... The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high 100 nH) can be printed on PCB load resonance frequency of the crystal. Normally, a value results for load-capacitance crystal. ATAM862-8 8 Output Power Measurement ...
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... ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 4590G–4BMCU–06/07 XTO VCO PFD 32 f PLL 4 Power up / down ATAM862 ANT1 Loop C1 Antenna 23 ANT2 C2 22 PA_ENABLE 21 f CLK BP60/T3O 20 OSC2 19 OSC1 18 BP50/INT6 S1 17 BP52/INT1 S2 16 BP53/INT1 S3 15 BP40/SC/INT3 ...
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... Figure 7-4. FSK Application Circuit C4 XTAL 1 C5 XTAL GND 3 ENABLE 4 NRESET 5 BP63/T3I 6 BP20/NTE 7 BP23 8 BP41/T2I/VMI 9 BP42/T2O 10 BP43/SD/ INT3 11 VSS 12 ATAM862-8 10 XTO VCO PFD 32 f PLL 4 Power up/down ANT1 Loop C1 Antenna C2 23 ANT2 22 PA_ENABLE 21 f CLK BP60/T3O 20 OSC2 19 OSC1 ...
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... V, -85°C to +125 C PA_ENABLE < 0.25 V, 25°C PA_ENABLE = > 1 < 0.25 V ENABLE PA_ENABLE = 3 > 1 > 1.7 V ENABLE PA_ENABLE = 3 amb = (166 + j226) Load ATAM862-8 ANT1 ANT2 XTAL ENABLE Min. Max. 5 100 150 -55 +125 -55 +125 (1) -0 0.3) S Value 135 Symbol Min. ...
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... Input current high Low level input voltage PA_ENABLE input High level input voltage Input current high Note higher than 3.6 V, the maximum voltage will be reduced to 3 ATAM862 25°C. All parameters are refered to GND (Pin 3). amb = -40°C to +85 C amb = 3 2 -40° ...
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... The microcontroller block is a member of Atmel’s family of 4-bit single-chip microcontrollers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multi- function timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on-chip clock generation with integrated RC-, 32-kHz and 4-MHz crystal oscillators. 4590G–4BMCU–06/07 4-bit RAM Data Memory ATAM862-8 13 ...
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... Differences between ATAM862-8 and ATAR862 Microconrtollers 14.1.1 Program Memory The program memory of the devices is realized as an EEPROM. The memory size for user pro- grams is 4096 bytes programmed as 258 LOCK-bit function is user-selectable and protects the device from unauthorized read-out of the program memory. ...
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... The following sections describe each functional block in more detail. 4590G–4BMCU–06/07 Reset Program memory Reset Instruction bus Clock Instruction decoder System clock Interrupt controller Sleep I/O bus On-chip peripheral modules ATAM862-8 MARC4 CORE 256 x 4-bit RP Memory bus TOS CCR ALU RAM 15 ...
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... The microcontroller instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a user definable location and maximum depth. ATAM862-8 16 FFFh ROM ...
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... RAM (256 x 4-bit) Autosleep FCh TOS-1 RP 04h 00h 16-3 TOS CCR ATAM862-8 Expression stack 3 0 FFh TOS TOS-1 TOS-2 Global variables 4-bit Expression Return stack stack 11 Return stack Global v 07h variables 03h 12-bit 0 Program counter ...
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... Boolean operations have no effect on the C-flag. 16.3.9 Branch (B) The branch flag controls the conditional program branching. Should the branch flag has been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arith- metic, logic, shift, and rotate operations. ATAM862-8 18 4590G–4BMCU–06/07 ...
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... Most of the instructions are only one byte long and are exe- cuted in a single machine cycle. For more information refer to the “MARC4 Programmer’s Guide”. 4590G–4BMCU–06/07 RAM SP TOS-1 TOS-2 TOS-3 TOS-4 CCR “Peripheral Modules” on page ATAM862-8 TOS ALU 32. The I/O bus is internal “Emulation” on page 104). 19 ...
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... Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou- tine being activated. This is extremely short (taking between machine cycles depending on the state of the core). ATAM862-8 20 Table 16-1 on page 21). The programmer can postpone the “Peripheral Modules” on ...
Page 21
... D8h (SCALL 0C0h) 100h E8h (SCALL 100h) 140h E8h (SCALL 140h) 180h F0h (SCALL 180h) 1C0h F8h (SCALL 1C0h) 1E0h FCh (SCALL 1E0h) ATAM862-8 RTI INT2 active RTI SWI0 INT0 pending INT0 active RTI Autosleep Function Software interrupt (SWI0) External hardware interrupt, any edge at BP52 or ...
Page 22
... Hardware Interrupts In the microcontroller block, there are eleven hardware interrupt sources with seven different lev- els. Each source can be masked individually by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in ATAM862-8 22 Interrupt Mask Bit P52M1, P52M2 P5CR ...
Page 23
... Two values for the brown-out voltage threshold are programmable via the BOT bit in the SC register. 4590G–4BMCU–06/07 Figure 17-1). A master reset activation will reset the V DD Pull-up NRST ATAM862 additional DD during reset by any SS Table 21-1 on page CL Reset Internal ...
Page 24
... V below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS bit is set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the VMC register. ATAM862 ...
Page 25
... Not allowed Voltage Interrupt Mask bit VIM = 0, voltage monitor interrupt is enabled VIM = 1, voltage monitor interrupt is disabled Voltage Monitor Status bit VMS = 0, the voltage at the comparator input is below V VMS = 1, the voltage at the comparator input is above V ATAM862 INT7 OUT VIM - res VMS Primary register address: " ...
Page 26
... Clock Module The ATAM862-8 contains a clock module with 4 different internal oscillator types: two RC-oscil- lators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1 and OSC2 are the interface to connect a crystal either to the 4-MHz the 32-kHz crystal oscillator. ...
Page 27
... BOT - - - OS1 OS0 Clock Modes Clock Source for SYSCL OS1 OS0 CCS = RC-oscillator 1 (internal RC-oscillator 1 (internal RC-oscillator 1 (internal RC-oscillator 1 (internal) ATAM862-8 RC oscillator 1 IN1 RCOut1 Cin Control / IN2 Divide r Sleep WDL Cin/16 CM: NSTOP CCS CSS1 CSS0 CCS = 0 ...
Page 28
... OSC1 and V lator 2 frequency can be maintained stable with a tolerance of ±10% over the full operating temperature and a voltage range V For example: An output frequency at the RC-oscillator MHz can be obtained by connecting a resistor R = 360 k (see ext ATAM862-8 28 oscillator 1 OSC1 Ext. Clock or OSC2 Ext ...
Page 29
... oscillator 2 ext RcOut2 OSC1 R Trim Stop OSC2 OSC1 Oscin 4Out * XTAL 4-MHz 4 MHz oscillator C1 Stop Oscout OSC2 * * C2 Configurable C3 OSC1 Oscin * 4Out Cer. 4-MHz Res oscillator C1 Stop Oscout OSC2 * Configurable ATAM862-8 RcOut2 Osc-Stop 4Out Osc-Stop 4Out Osc-Stop 29 ...
Page 30
... Clock Management The clock management register controls the system clock divider and synchronization stage. Writing to this register triggers the synchronization cycle. 19.3.1 Clock Management Register (CM) CM: NSTOP CCS CSS1 CSS0 Table 19-3. ATAM862-8 30 OSC1 * XTAL 32 kHz C1 OSC2 * * C2 Configurable Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta- bilize oscillation before the oscillator output is used as system clock ...
Page 31
... syscl Sleep DD active total and f DD syscl ATAM862-8 Primary register address: "3"hex Bit 0 OS0 Reset value: 1x11b Selected Oscillators RC-oscillator 1 and external input clock RC-oscillator 1 and RC-oscillator 2 RC-oscillator 1 and 4-MHz crystal oscillator RC-oscillator 1 and 32-kHz crystal oscillator ) 31 ...
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... In this case, a bank subport registers are indirectly addressed with the subport address. The first OUT instruction writes the subport address to the sub address register, the second IN or OUT instruction reads data from or writes data to the addressed subport. ATAM862-8 32 Power-down Modes ( ...
Page 33
... Addr. (M1) IN (lo) Prim._Data(hi) = Data to be written into Auxiliary Register (high nibble) SPort_Data(lo) = Data to be written into SubPort (low nibble) SPort_Data(hi) = Data to be written into SubPort (high nibble) (lo) = SPort_Data (low nibble) (hi) = SPort_Data (high nibble) ATAM862-8 Module M3 Primary Reg. Primary Reg other modules ...
Page 34
... T3CS 2 T3CM1 3 T3CM2 4 T3CO1 4 T3CP 5 T3CO2 6 7-F C T3C T3ST D, E – F VMC VMST ATAM862-8 34 Write/ Read Reset Value Register Function W/R 1xx1b Port 1 - data register/input data W/R 1111b Port 2 - data register/pin data W 1111b Port 2 - control register W 1x11b System configuration register R xxxxb Watchdog reset W ...
Page 35
... DROP removes the first invalid nibble. The second IN reads the valid pin state. Use an OUT instruction followed instruction. Via the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up/pull-down configuration. Write a "1" for pins with pull-up resistors and a "0" for pins with pull-down resistors. ATAM862-8 Figure 22-1 35 ...
Page 36
... To avoid any conflict with the optional internal pull-down transistors, BP20 handles the pull-down options in a different way than all other ports. BP20 is the only port that switches off the pull-down transistors during reset. ATAM862-8 36 I/O Bus (Data out) ...
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... Bit 1 Bit 0 P2CR2 P2CR1 P2CR0 Port 2 Control Register Function BP20 in input mode BP20 in output mode BP21 in input mode BP21 in output mode BP22 in input mode BP22 in output mode BP23 in input mode BP23 in output mode ATAM862 Switched Static pull-up Pull- BP2y ...
Page 38
... Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a byte-wide register and is configured by writing first the low nibble and then the high nibble (see section Figure 22-3. Bi-directional Port 5 Figure 22-4. Port 5 External Interrupts BP52 BP53 ATAM862-8 38 “Addressing Peripherals” on page I/O Bus (Data out) I/O Bus D ...
Page 39
... ATAM862-8 Primary register address: "5"hex Bit 0 Reset value: 1111b Auxiliary register address: "5"hex Bit 1 Bit 0 P50M2 P50M1 Reset value: 1111b ...
Page 40
... PIn POut I/O Bus Master reset I/O Bus PDir 22.4.1 Port 4 Data Register (P4DAT) Bit 3 P4DAT3 22.4.2 Port 4 Control Register (P4CR) Byte Write First write cycle Second write cycle P4xM2, P4xM1 – Port 4x Interrupt mode/direction code ATAM862-8 40 Figure PxMRy D Q PxDATy S (Direction PxCRy * Configurable ...
Page 41
... Two additional multiplexes allow data and port direction control to be Bit 2 Bit 1 Bit P6DAT0 Bit 2 Bit 1 Bit 0 P63M1 P60M2 P60M0 ATAM862-8 Second Write Cycle Code Function BP42 in input mode BP42 in output mode BP42 enable alternate function (T2O for Timer ...
Page 42
... The SSI operates as two wire serial interface or as shift register for modulation and demodulation. The modulator and demodulator units work together with the timers and shift the data bits into or out of the shift register. There is a multitude of modes in which the timers and the serial interface can work together. ATAM862-8 42 Port 6 Control Register Function ...
Page 43
... Compare 3/2 Timer 2 TOG3 4-bit Counter 2/1 MUX Compare 2/1 Control POUT 8-bit Counter 2/2 MUX DCG Compare 2/2 SSI TOG2 Receive buffer 8-bit shift register MUX Transmit buffer ATAM862-8 NRST Watchdog INT2 Control Demodu- lator 3 Modu- lator 3 INT5 Modu- lator 2 I/O bus INT4 SCL Control INT3 ...
Page 44
... The watchdog timer operation mode and the time interval for the watchdog reset can be pro- grammed via the watchdog control register (WDC). Figure 22-7. Timer 1 Module Figure 22-8. Timer 1 and Watchdog Write of the T1C1 register CL1 ATAM862-8 44 SYSCL CL1 Prescaler MUX SUBCL T1CS ...
Page 45
... SUBCL/ 256 SUBCL/256 1 0 2048 SUBCL/2048 1 1 16384 SUBCL/16384 ATAM862-8 Address: "7"hex - Subaddress: "8"hex Reset value: 1111b Time Interval with Time Interval with SUBCL = 32 kHz SYSCL = 2/1 MHz 61 µs 1 µs/2 µs 122 µs 2 µs/4 µs 244 µs 4 µs/8 µs 488 µ ...
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... Bit 3 -> MSB, Bit 0 -> LSB WDL WDR WDT1 WDT0 Both these bits control the time interval for the watchdog reset. Table 22-6. WDT1 ATAM862-8 46 Bit 2 Bit 1 Bit 0 T1BP T1CS T1IM Timer 1 SUBCL ByPassed T1BP = 1, TIOUT = T1MUX T1BP = 0, T1OUT = SUBCL Timer 1 input Clock Select ...
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... For 12-bit compare data value: For 8-bit compare data value: For 4-bit compare data value: 4590G–4BMCU–06/ 4095 255 ATAM862-8 47 ...
Page 48
... The duty cycle gen- erator (DCG) has to be bypassed in this mode. Figure 22-10. 12-bit Compare Counter CL2/1 4-bit counter RES 4-bit compare CM1 4-bit register ATAM862-8 48 P4CR T2M1 CL2/2 DCG OVF1 POUT RES ...
Page 49
... T2D1, 0 T2RM CL2/2 DCG 8-bit counter 8-bit compare 8-bit register P41M2, 1 T2D1, 0 CL2/1 4-bit counter MUX 4-bit compare 4-bit register T2CS1, 0 ATAM862-8 Timer 2 output mode and T2OTM-bit T2OTM T2IM T2CTM OVF2 RES CM2 Timer 2 output mode and T2OTM-bit T2RM T2OTM T2IM ...
Page 50
... Figure 22-13. Timer 2 Modulator Output Stage CONTROL 22.11 Timer 2 Output Signals 22.11.1 Timer 2 Output Mode 1 Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Figure 22-14. Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge ATAM862-8 50 DCGO SO TOG2 RE Biphase/ Manchester ...
Page 51
... A Timer 2 compare match toggles the output flip-flop (M2) -> T2O Is Set Input Counter 2 T2R Counter 2 CMx INT4 T2O Toggle by start T2O Input Counter 2 T2R Counter 2 CMx OVF2 INT4 T2O 4095 255 4095 255 ATAM862 ...
Page 52
... Timer 2 Output Mode 4 Biphase Modulator: Timer 2 modulates the SSI internal data output (SO) to Biphase code Figure 22-19. Biphase Modulation ATAM862-8 52 DCGO TOG2 ...
Page 53
... SO Bit T2O Bit 7 Data: 00110101 T2R 255 0 CM2 OVF2 load the next compare value INT4 T2O ATAM862-8 8-bit SR-Data Bit Bit 0 100 255 0 150 255 0 50 T2CO2=150 load load ...
Page 54
... Timer 2 Mode Register 1 (T2M1) Bit 3 T2D1 T2D1 T2D0 Table 22-8. T2D1 T2MS1 T2MS0 ATAM862-8 54 Bit 2 Bit 1 Bit 0 T2CS0 T2TS T2R Timer 2 Clock Select bit 1 Timer 2 Clock Select bit 0 Timer 2 Clock Select T2CS0 Input Clock (CL 2/1) of Counter Stage 2/1 0 System clock (SYSCL) ...
Page 55
... T2TOP = 1, sets toggle outputs with the write cycle ( Note: If T2R = 1, no output preset is possible Timer 2 Output Select bit 2 Timer 2 Output Select bit 1 Timer 2 Output Select bit 0 ATAM862-8 Timer 2 Modes 12-bit compare counter; the DCG has to be bypassed in this mode 8-bit compare counter with 4-bit ...
Page 56
... In the 12-bit timer mode, T2CO1 contains bits and T2CO2 bits the 12-bit com- pare value. In all other modes, the two compare registers work independently and 8-bit compare register. When assigned to the compare register a compare event will be suppressed. ATAM862-8 56 T2OS2 T2OS1 ...
Page 57
... T2OTM Bit 3 Bit 2 Bit 1 Bit 3 Bit 2 Bit 1 Bit 7 Bit 6 Bit 5 ATAM862-8 Address: "7"hex - Subaddress: "3"hex Reset value: 0000b T2CTM Timer 2 Interrupt Source x Compare match (CM2) x Overflow (OVF2) 1 Compare match (CM2) Address: "7"hex - Subaddress: "4"hex Bit 0 Reset value: 1111b Address: " ...
Page 58
... This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via its capture register while it is running. In capture mode, the counter value can be captured by a programmable capture event from the Timer 3 input or Timer 2 output. ATAM862-8 58 TOG2 T3I ...
Page 59
... Via the Timer 3 clock-select register, the internal or external clock source can be selected. This register selects also the active edge of the external input. An edge at the external input T3I can generate also an interrupt if the T3EIM-bit is set and the Timer 3 is stopped (T3R = 0) in the T3C-register. 4590G–4BMCU–06/07 ATAM862-8 59 ...
Page 60
... The selected clock from an internal or external source increments the 8-bit counter. In this mode, the timer can be used as event counter for external clocks at T3I or as timer for generating inter- rupts and pulses at T3O. The counter value can be read by the software via the capture register. Figure 23-3. Counter Reset with Each Compare Match ATAM862-8 60 TOG2 T3I ...
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... CM31 CM32 Toggle by start T3O T3R T3EX CM31 CM32 T3O ATAM862 ...
Page 62
... Timer 3 – Mode 5: Timer/Counter, External Trigger Restart and External Capture (with T3I Input) The Timer 3 runs as timer/counter in mode 2, but its output T3O is used as output for the Timer 2 output signal. ATAM862-8 62 “Combination Mode 10: Frequency Measurement or Event Counter with Time 91). T3R ...
Page 63
... T3R CM31 CM32 0 SO T3O ATAM862-8 92). “Combination Mode 12: Burst Modula- “Combination Mode 12: Burst Modulation 2” ...
Page 64
... The compare register 2 can also be used to detect a time-out error and handle it with an interrupt routine (see page 89). Figure 23-10. Manchester Demodulation CM31=SCI ATAM862-8 64 TOG2 SIR 0 SO SCO ...
Page 65
... Timer 3 Synchronize mode T3I T3EX Q1=SI Reset Counter 3 0 BIT 0 T3R T3I 1011 121314 16 T3CP- Capture value = X Register ATAM862-8 Biphase demodulation mode BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 15 171819 ...
Page 66
... Timer 2 must be used in mode 3 and the prescaler stage must be supplied by the internal shift clock of the shift register. Figure 23-13. Modulator 3 23.5 Timer 3 Demodulator for Biphase, Manchester and Pulse-width-modulated Signals The demodulator stage of Timer 3 can be used to decode Biphase, Manchester and pulse-width-coded signals. Figure 23-14. Timer 3 Demodulator 3 ATAM862 TOG3 Set Res T3TOP SO ...
Page 67
... In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI modes are not allowed. ATAM862-8 Address: "B"hex - Subaddress: "0"hex Reset value: 1111b Timer 3 Modes Timer/counter with a read access Timer/counter, external capture and external trigger ...
Page 68
... T3TOP T3TS T3R 23.6.3 Timer 3 Status Register 1 (T3ST) Read Read T3ED T3C2 T3C1 Note: ATAM862-8 68 Bit 3 Bit 2 Bit 1 T3EIM T3TOP T3TS Timer 3 Edge Interrupt Mask T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I) T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I) Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to " ...
Page 69
... Timer 3 Clock Select Bits TCS0 Counter 3 Input Signal (CL3 System clock (SYSCL Output signal of Timer 2 (POUT Output signal of Timer 1 (T1OUT External input signal from T3I edge detect ATAM862-8 Address: "B"hex - Subaddress: "1"hex Bit 0 T3CS0 Reset value: 1111b 69 ...
Page 70
... T3CM1 contains the mask bits for the match event of the Counter 3 compare register 1. 23.6.7 Timer 3 Compare Mode Register 2 (T3CM2) T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 ATAM862-8 70 Bit 3 Bit 2 Bit 1 T3SM1 T3TM1 T3RM1 Timer 3 Single action Mask bit 1 T3SM1 = 0, disables single-action compare mode T3SM1 = 1, enables single-compare mode ...
Page 71
... Bit 3 Bit 2 Bit15 Bit 0 Address: "B"hex - Subaddress: "4"hex High Nibble Bit 7 Bit 6 Bit 5 Bit 4 Low Nibble Bit 3 Bit 2 Bit15 Bit 0 ATAM862-8 Reset value: 1111b Reset value: 1111b Reset value: 1111b Reset value: 1111b Reset value: xxxxb Reset value: xxxxb 71 ...
Page 72
... Serial demodu- lated data can be serially captured in the SSI and read by the controller. In the Timer 3 modes 10 and 11 (demodulation modes) the SSI can only be used as demodulator. ATAM862-8 72 packaging solutions 4590G–4BMCU–06/07 ...
Page 73
... MCL mode, an additional acknowledge bit is appended to the end of the telegram for handshaking purposes (see 4590G–4BMCU–06/07 I/O-bus SIC1 SIC2 SC SSI-Control SO /2 8-bit Shift Register MSB Shift_CL STB Transmit Buffer “MCL Bus Protocol” on page ATAM862-8 Timer 2 / Timer 3 SISC SI SCI SO Control INT3 Output SI LSB SRB Receive Buffer I/O-bus 77). SC ...
Page 74
... At the same time an interrupt (if enabled) is generated. The SSI then continues shift- ing in the following 8-bit telegram. If, during this time the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer ATAM862 ...
Page 75
... SC msb lsb msb data 1 rx data 2 SIR ACT ATAM862-8 msb lsb msb data 2 tx data 3 Write STB Write STB (tx data 2) (tx data 3) lsb msb ...
Page 76
... SIR bit. So, if the SIR bit is set to ‘1’ in telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition. Figure 23-19. Example of MCL Transmit Dialog SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) ATAM862-8 76 Start SC msb lsb ...
Page 77
... Start SC msb lsb data 1 ACT SIR SDD Write STB (tx data bus. Each slave receives this address and compares it with ATAM862-8 Stop msb lsb data 2 Read SRB (rx data 2) 77 ...
Page 78
... In either case this interrupt is capable of waking the con- troller out of sleep mode. To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and the Inter- rupt Function (IFN) while the Port 4 interrupts are enabled by setting appropriate control bits in P4CR register. ATAM862-8 78 (1) (2) (4) ...
Page 79
... OMSK signal and all following data bits are blanked. Figure 23-23. SSI Output Masking Function TOG2 POUT T1OUT SYSCL 4590G–4BMCU–06/07 CL2/1 4-bit counter 2/1 SCL Compare 2 Shift_CL ATAM862-8 Timer 2 CM1 OMSK Control SSI-control 8-bit shift register MSB LSB SO Output SI 79 ...
Page 80
... In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). • Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only). • In MCL modes, writing SIR generates a start condition and writing a 1 generates a stop condition. ATAM862-8 80 Bit 2 Bit 1 Bit 0 SCD ...
Page 81
... SDD = 0, receive mode SD line used as input (receive data). SRDY is set ...... ...... by a receive buffer read access SDD controls port directional control and defines the reset function for the SRDY-flag ATAM862-8 Auxiliary register address: "A"hex Reset value: 1111b 81 ...
Page 82
... Serial Transmit Buffer (STB) – Byte Write First write cycle Second write cycle T he STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift regi star ts shifting with ATAM862-8 82 Bit 3 Bit 2 Bit 1 MCL RACK SIM - - - ...
Page 83
... SIC2 TOG2 SCLI POUT SSI-control T1OUT SYSCL SCL SO 8-bit shift register MSB Shift_CL STB Transmit buffer ATAM862-8 Primary register address: "9"hex Bit 4 Reset value: xxxxb Bit 0 Reset value: xxxxb I/O-bus T2M2 DCGO 8-bit counter 2/2 Output RES OVF2 TOG2 Compare 2/2 MOUT ...
Page 84
... Counter 2 24.1.2 Combination Mode 2: Biphase Modulation 1 SSI mode 1: Timer 2 mode Timer 2 output mode 4: Figure 24-3. Biphase Modulation 1 ATAM862-8 84 8-bit NRZ and internal data SO output to the Timer 2 modulator stage 8-bit compare counter with 4-bit programmable prescaler and DCG Duty cycle burst generator ...
Page 85
... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit MSM Timer 2 Mode 3 SCL Counter 2/1 = Compare Register 2 OMSK T2O ATAM862-8 8-bit SR-data Bit Bit 0 Figure 24-5 shows an example for a 0 ...
Page 86
... The SSI has a special mode to supply the prescaler via the shift clock. The control output signal (OMSK) of the SSI is used as stop signal for the modulator. 13-bit Biphase telegram. Figure 24-6. Biphase Modulation 2 Counter 2/1 ATAM862-8 86 8-bit shift register internal data output (SO) to the Timer 2 modulator stage 8-bit compare counter and 4-bit prescaler ...
Page 87
... I/O-bus CP3 T3CP 8-bit counter 3 T3C Compare 3/2 Timer 3 - control T3CO2 T3CM1 SIC1 SIC2 SCLI SSI-control SO 8-bit shift register MSB Shift_CL STB Transmit buffer I/O-bus ATAM862-8 T3M T3EX T3I Demodu- lator 3 CM31 RES INT5 T3ST TOG3 SO Modulator 3 Control M2 T3CM2 SI SC SISC Control ...
Page 88
... Timer 3. The SSI must be supplied with the toggle signal of Timer 2. The counter is driven by an internal or external clock source. Figure 24-9. Pulse-width Modulation Counter 3 ATAM862-8 88 8-bit shift register internal data output (SO) to the Timer 3 FSK modulation with shift register data (SO) ...
Page 89
... Timer 3 Manchester demodulation/pulse-width demodulation with Timer 3 Timer 3 Synchronize mode T3I T3EX SI 1 SR-DATA Bit 7 ATAM862-8 Manchester demodulation mode Bit 6 Bit 5 Bit 4 ...
Page 90
... The counter can be driven by any internal clock source and the output T3O can be used by Timer 2 in this mode. Figure 24-11. Biphase Demodulation CM31=SCI SR-DATA ATAM862-8 90 8-bit shift register internal data input (SI) and the internal shift clock (SCI) from the Timer 3 Biphase demodulation with Timer 3 ...
Page 91
... Timer 2 TOG2-signal) T3M T3EX T3I Demodu- lator 3 CM31 RES INT5 T3ST TOG3 SO Control Modulator 3 TOG2 M2 T3CM2 I/O-bus T2M2 OUTPUT OVF2 MOUT TOG2 Compare 2/2 Biphase-, INT4 Manchester- modulator T2CO2 SO Control SSI (RE, FE, SCO, OMSK) ATAM862-8 SCI SI T3O SSI T2O M2 Timer 2 modulator 2 output-stage 91 ...
Page 92
... Counter 3 CM1 CM2 TOG3 Counter 2/2 TOG2 M2 T3O ATAM862-8 92 T3R T3I 11121314151617 TOG2 T3CP- Capture value = 0 Register T3R T3I ...
Page 93
... POUT RES Timer 2 - control Compare 2/2 CM1 POUT T2CM SIC1 SIC2 TOG2 SCLI SSI-control SO SCL 8-bit shift register MSB Shift_CL STB Transmit buffer I/O-bus ATAM862-8 T3M T3EX Demodu- T3I lator 3 CM31 RES INT5 T3ST TOG3 SO Modulator 3 Control M2 TOG2 T3CM2 I/O-bus T2M2 OUTPUT ...
Page 94
... The compare- and compare mode registers must be programmed to generate the two frequen- cies via the output toggle flip-flop. The SSI can be supplied with the toggle signal of Timer 2 or any other clock source. The Timer 3 counter is driven by an internal or external clock source. ATAM862-8 94 8-bit shift register internal data output (SO) to the Timer 3 ...
Page 95
... Counter 3 CM31 CM32 0 SO T3O Timing control Page Address control Page Mode control SCL I/O control SDA ATAM862-8 1 HV-generator --> Write "01h" EEPROM --> Write "09h" 16-bit read/write buffer 8-bit data register ...
Page 96
... The control byte that follows the START condition determines the following operation. It consists of the 5-bit row address, 2 mode control bits and the READ/NWRITE bit that is used to control the direction of the following transfer. A "0" defines a write access and a "1" a read access. ATAM862-8 96 SCL SDA ...
Page 97
... If the cycle is complete, it returns an acknowledge and the master can proceed with the next read or write cycle. 4590G–4BMCU–06/07 EEPROM Address Control byte Ackn Data byte 512 bits and is organized 16-bit matrix each. To read ATAM862-8 Mode Control Read/ Bits NWrite C1 C0 R/NW Ackn Ackn Data byte Ackn Stop ...
Page 98
... If the memory address limit is reached, the data word address will roll over and the sequential read will continue. The master can terminate the read operation after every byte by not responding with an acknowledge (N) and by issuing a stop condition. ATAM862-8 98 Control byte ...
Page 99
... Data byte 1 N Control byte A Data byte 1 A Control byte A Data byte 1 A MSB A4 A3 Row address LB(R) HB(R) LB(R+1) MSB A4 A3 Row address HB(R) LB(R) HB(R-1) "FFh" A Stop ATAM862-8 Stop Data byte 2 N Stop Data byte Data byte HB(R+ LB(R+ ...
Page 100
... RC oscillator active, 4-MHz quartz oscillator active) Sleep current (CPU sleep, 32-kHz quartz oscillator active 4-MHz quartz oscillator inactive) Sleep current (CPU sleep, 32-kHz quartz oscillator inactive 4-MHz quartz oscillator inactive) Pin capacitance ATAM862-8 100 ). DD Symbol short T amb ...
Page 101
... ATAM862-8 Symbol Min. Typ. Max. V 1.54 1.7 1.88 POR V 1.83 2.0 2.20 POR V 50 POR V 3.0 3.35 MThh V 2.77 3.0 MThh V 2.6 2.9 MThm V 2.4 2.6 MThm V 2.2 2.44 MThl V 2.0 2.2 MThl V 1.3 1.44 VMI V 1.18 1.3 VMI ...
Page 102
... RC Oscillator 1 Frequency Stability – RC Oscillator 2 External Resistor Frequency Stability Stabilization time 4-MHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) ATAM862-8 102 = unless otherwise specified. SS amb Test Conditions V = 1 -40 to +125 C amb V = 2 ...
Page 103
... C /C programmable IN OUT Erase-/write cycles T = 125 C amb For 16-bit access T = 125 C amb Erase-/write cycles amb OSCIN OSCOUT SCLIN SCLOUT ATAM862-8 Symbol Min. Typ. Max. f 32.768 X t 0.5 SQ f/f - OUT f 32 ...
Page 104
... The designer also gains the ability to analyze the executed instruction sequences and all the I/O activities. Figure 30-1. MARC4 Emulation MARC4 emulator Program memory Trace memory Control logic Personal computer ATAM862-8 104 MARC4 emulation-CPU I/O bus CORE I/O control Emulation control Port 0 Port 1 SYSCL/ ...
Page 105
... Drawing-No.: 6.543-5056.02-4 Issue: 1; 07.06.01 4590G–4BMCU–06/07 Program Memory Data-EEPROM 4 kB Flash Flash 2 8.05 -0.25 0.65 ±0.05 7.15 ±0. ATAM862-8 Package Delivery 512 bit SSO24 Taped and reeled 512 bit SSO24 Tubes 5.4 ±0.2 4.4 ±0.1 6.45 ±0.15 Package: SSO24 Dimensions in mm technical drawings according to DIN ...
Page 106
... Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4590G-4BMCU-04/07 4590F-4BMCU-12/05 4590E-4BMCU-09/04 ATAM862-8 106 History Put datasheet in new template Features on page 1: Maximum output power value and the low current value are changed Put datasheet in new template Page 30: Section “ ...
Page 107
... Introduction ............................................................................................ 13 15 MARC4 Architecture General Description ........................................... 15 16 Components of Microcontroller Core .................................................. 15 17 Program Memory ................................................................................... 16 4590G–4BMCU–06/07 7.1 ASK Transmission ................................................................................................6 7.2 FSK Transmission ................................................................................................6 7.3 CLK Output ..........................................................................................................7 7.4 Application Circuit ................................................................................................8 14.1 Differences between ATAM862-8 and ATAR862 Microconrtollers ....................14 17.1 RAM ...................................................................................................................16 17.2 Registers ............................................................................................................17 17.3 ALU ....................................................................................................................19 17.4 I/O Bus ...............................................................................................................19 17.5 Instruction Set ....................................................................................................19 17.6 Interrupt Structure ..............................................................................................20 17.7 Software Interrupts .............................................................................................22 ATAM862-8 107 ...
Page 108
... Master Reset ........................................................................................... 23 19 Voltage Monitor ...................................................................................... 24 20 Clock Generation ................................................................................... 26 21 Power-down Modes ............................................................................... 31 22 Peripheral Modules ................................................................................ 32 23 Bi-directional Ports ................................................................................ 35 24 Timer 3 .................................................................................................... 58 ATAM862-8 108 17.8 Hardware Interrupts ...........................................................................................22 18.1 Power-on Reset and Brown-out Detection .........................................................23 20.1 Clock Module .....................................................................................................26 20.2 Oscillator Circuits and External Clock Input Stage .............................................27 20.3 Clock Management ............................................................................................30 22.1 Addressing Peripherals ......................................................................................32 23 ...
Page 109
... Serial Interface Registers ...................................................................................80 25.1 Combination Mode Timer 2 and SSI ..................................................................83 25.2 Combination Mode Timer 3 and SSI ..................................................................87 25.3 Combination Mode Timer 2 and Timer 3 ............................................................91 25.4 Combination Mode Timer 2, Timer 3 and SSI ....................................................93 25.5 Data EEPROM ...................................................................................................95 25.6 Serial Interface ...................................................................................................96 25.7 EEPROM ............................................................................................................97 25.8 Initialization the Serial Interface to the EEPROM ...............................................99 ATAM862-8 109 ...
Page 110
... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...