atam862-8 ATMEL Corporation, atam862-8 Datasheet - Page 75
atam862-8
Manufacturer Part Number
atam862-8
Description
Atam862-8 Microcontroller With Uhf Ask/fsk Transmitter
Manufacturer
ATMEL Corporation
Datasheet
1.ATAM862-8.pdf
(110 pages)
- Current page: 75 of 110
- Download datasheet (3Mb)
4590G–4BMCU–06/07
and the SSI will continue clocking in the next telegram. Should, however, the first telegram not
have been read (SRDY = 1), then the SSI will stop, temporarily holding the second telegram in
the shift register until a certain point of time when the controller is able to service the receive
buffer. In this way no data is lost or overwritten.
Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and latch the
present contents of the shift register into the receive buffer. This can be used for clocking in a
data telegram of less than 8 bits in length. Care should be taken to read out the final complete
8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and termi-
nating the reception. After termination, the shift register contents will overwrite the receive
buffer.
Figure 23-17. Example of 8-bit Synchronous Transmit Operation
Figure 23-18. Example of 8-bit Synchronous Receive Operation
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
ACT
(IFN = 0)
(IFN = 1)
SIR
Interrupt
Interrupt
SD
SC
SRDY
ACT
SIR
SD
SC
msb
7 6 5
Write STB
(tx data 1)
rx data 1
4 3 2 1 0
msb
7 6 5 4 3 2 1
tx data 1
lsb
msb
7 6 5
lsb
rx data 2
0
4 3 2 1 0
Write STB
(tx data 2)
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
Write STB
(tx data 3)
tx data 2
Read SRB
(rx data 1)
lsb msb
msb
7 6 5 4 3 2 1 0
Read SRB
(rx data 2)
rx data 3
tx data 3
ATAM862-8
lsb
lsb
Read SRB
(rx data 3)
0
7 6 5 4
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