atam510 ATMEL Corporation, atam510 Datasheet - Page 33

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atam510

Manufacturer Part Number
atam510
Description
Marc4 4-bit Mtp Universal Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
3.3.1
3.3.1.1
4711B–4BMCU–01/05
Interval Timer Registers
Interval Timer Interrupt Priority Register (ITIPR)
Figure 3-9.
The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address
register of the prescaler/interval timer address ('F'hex) and the Interval Timer Interrupt Priority
Register (ITIPR) to the corresponding auxiliary register. The interrupt masks MIA and MIB
enable interrupt masking of INTA and INTB respectively. Each interrupt source can be pro-
grammed with PRA and PRB to one of two interrupt priority levels. Disabling both interrupts
resets the interval timer.
PRB - Priority select Interval Timer Interrupt INTB
PRA - Priority select Interval Timer Interrupt INTA
MIB - Mask Interval Timer Interrupt INTB
MIA - Mask Interval Timer Interrupt INTA
ITIPR
(e.g. SUBCL = 32 kHz)
INT5
INT1
INT6
INT2
ITIPR
Interval Timers/Prescaler
SUBCL
PRB
Bit 3
PRB
PRA
CK
R
8092 Hz
PRA
Bit 2
2
MIB
2
4096 Hz
2
3
MIA
2048 Hz
2
4
Bit 1
MIB
INTB
8:1
Mux
1024 Hz 256 Hz
2
15-stage binary counter
5
Buffer
Dh
Ch
Ah
Fh
Eh
Bh
9h
8h
2
ITFSR
6
2
7
Auxiliary register address (write only): 'F'hex
Bit 0
MIA
128 Hz
4096 Hz
1024 Hz
8 Hz
64 Hz
2
FS3
2048 Hz
256 Hz
8192 Hz
16 Hz
8
64 Hz
2
9
FS2
32 Hz
2
10
INTA
8:1
Mux
FS1
16 Hz
2
11
Buffer
Reset value: 1111b
8 Hz
2
7h
6h
5h
4h
3h
2h
1h
0h
FS0
12
4 Hz
2
13
16 Hz
4 Hz
1 Hz
2 Hz
64 Hz
2
ATAM510
14
8 Hz
32 Hz
2 Hz
128 Hz
1 Hz
2
15
33

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