ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 12

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

ML675200/ML67Q5200
External RAM/RAM Write Cycle
(V
1.
2.
12
ROMCS_N pulse width
RAMCS_N pulse width
ROMCS_N output hold time 2
RAMCS_N output hold time 2
XA[19:1] hold time 2
XBS_N[1:0] hold time 2
XWE_N output delay time
XWE_N output delay time pulse width
XD[15:0] output delay time
XD[15:0] output hold time
DD_CORE
n
Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the ROMAC/RAMAC registers.
t
XDOD
0
• Oki Semiconductor
= address setup time, n
and t
= 1.65 V to 1.95 V, V
XWED
are defined as a time period that starts from the point of change in ROMCS_N/RAMCS_N, XA[19:0], or XBS_N[1:0], whichever signal changes last.
Parameter
1
= XOE_N/XWE_N pulse width, Tc = HCLK cycle.
XBS_N[1:0]/PIOC[9:8]
XD[15:0]/PIOA[15:0]
XA[19:1]/PIOC[2:0]
ROMCS_N/PIOC[3]
RAMCS_N/PIOC[4]
XWE_N/PIOC[7]
DD_IO
PIOB[15:0]
= 2.7 V to 3.6 V, T
t
t
t
t
t
t
t
t
t
t
XROMCSW
XRAMCSW
XROMCSH2
XRAMCSH2
XAH2
XBH2
XWED
XWEW
XDOD
XDOH
[1]
Symbol
[2]
[2]
Figure 3. External ROM/RAM Write Cycle Timing
A
t
XDOD
= –30°C to +70°C)
t
XWED
Condition
CL = 50 pF
t
XROMCSW
, t
t
XRAMCSW
XWEW
(n
(n
0
0
+n
+n
n
n
0
1
1
1
Tc - 5
Tc - 10
Tc - 10
Min
+1)Tc - 10
+1)Tc - 10
—
Tc
Tc
-5
-5
t
t
XAH2
t
XDOH
BH2
t
XROMCSH2
Typ
—
—
—
—
—
—
—
—
—
—
, t
XRAMCSH2
n
0
Tc + 10
Max
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns