ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 17

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

External I/O Bus Write Cycle
(V
1.
2.
IOCS_N pulse width
IOCS_N output hold time 2
XA[19:1] hold time 2
XBS_N[1:0] hold time 2
XWE_N output delay time
XWE_N output delay time pulse width
XD[15:0] output delay time
XD[15:0] output hold time
DD_CORE
n
Address setup time and XOE_N/XWE_N pulse width are parameters that can be set by the IOAC register.
t
XIODOD
0
= address setup time, n
and t
= 1.65 V to 1.95 V, V
XIOWED
Parameter
are defined as a time period that starts from the point of change in IOCS_N, XA[19:0], or XBS_N[1:0], whichever signal changes last.
1
= XOE_N/XWE_N pulse width, Tc = HCLK cycle
XBS_N[1:0]/PIOC[9:8]
XD[15:0]/PIOA[15:0]
XA[19:1]/PIOC[2:0]
XWE_N/PIOC[7]
IOCS_N/PIOC[5]
DD_IO
PIOB[15:0]
= 2.7 V to 3.6 V, T
[1]
t
t
t
t
t
t
t
t
XIOCSW
XIOCSH2
XIOAH2
XIOBH2
XIOWED
XIOWEW
XIODOD
XIODOH
Symbol
[2]
[2]
Figure 7. External I/O Bus Write Cycle Timing
A
t
XIOWED
t
= –30°C to +70°C)
XIODOD
Condition
C
L
= 50 pF
t
t
XIOWEW
XIOCSW
(n
0
+n
n
n
0
1
Tc - 3
Min
1
Tc - 5
Tc - 3
—
+1)Tc - 3
Tc
-3
-3
t
t
t
XIOCSH2
XIODOH
XIOBH2
t
XIOAH2
Typ
—
—
—
—
—
—
—
—
ML675200/ML67Q5200
Oki Semiconductor • 17
n
0
Max
Tc + 5
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns