z85c30 ZiLOG Semiconductor, z85c30 Datasheet - Page 44

• Manufacturer Part Number: z85c30
• Description: Cmos Scc Serial Communications Controller
• Manufacturer: ZiLOG Semiconductor

CMOS SCC Serial Communications Controller
Product Specification
40
Interrupt Acknowledge Cycle Timing
Figure 26
displays the Interrupt Acknowledge cycle timing. The address on AD7–AD0
and the state of CS0 and INTACK are latched by the rising edge of AS. If INTACK is
Low, the address and CS0 are ignored. The state of the R/W and CS1 are also ignored for
the duration of the Interrupt Acknowledge cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external IEI/IEO daisy chains settle. If there is an
interrupt pending in the SCC, and IEI is High when DS falls, the Acknowledge cycle was
intended for the SCC. In this case, the SCC is programmed to respond to RD Low by
placing its interrupt vector on D7-D0 and internally setting the appropriate Interrupt-
Under-Service latch.
AS
CS0
(Ignored)
INTACK
AD7–AD0
(Ignored)
Vector
DS
Figure 26. Interrupt Acknowledge Cycle Timing
PS011705-0608
Functional Description