mc68hc908qb4 Freescale Semiconductor, Inc, mc68hc908qb4 Datasheet - Page 202

• Manufacturer Part Number: mc68hc908qb4
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

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17.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
17.3.1.5 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal,
it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
17.3.1.6 Baud Rate
The monitor communication baud rate is controlled by the frequency of the external or internal oscillator
and the state of the appropriate pins as shown in
Table 17-1
bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in
forced monitor mode, the effective baud rate is the bus frequency divided by 335.
17.3.1.7 Commands
The monitor ROM firmware uses these commands:
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
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READ (read memory)
WRITE (write memory)
IREAD (indexed read)
IWRITE (indexed write)
READSP (read stack pointer)
RUN (run user program)
also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the
Wait one bit time after each echo before sending the next byte.
START
BIT
0
BIT 0
1
2
BIT 1
MISSING STOP BIT
3
Figure 17-13. Monitor Data Format
Figure 17-14. Break Transaction
4
BIT 2
MC68HC908QB8 Data Sheet, Rev. 2
5
6
BIT 3
7
BIT 4
NOTE
Table
BIT 5
17-1.
2-STOP BIT DELAY BEFORE ZERO ECHO
BIT 6
0
1
BIT 7
2
3
STOP
BIT
4
START
NEXT
5
BIT
6
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