mc68hc908lv8 Freescale Semiconductor, Inc, mc68hc908lv8 Datasheet
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... MC68HC908LV8 Data Sheet M68HC08 Microcontrollers MC68HC908LV8 Rev. 2 12/2005 freescale.com ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev ...
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... Revision History Revision History Revision Date Level December, 2 First general release. 2005 4 Description MC68HC908LV8 Data Sheet, Rev. 2 Page Number(s) N/A Freescale Semiconductor ...
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... Chapter 12 Keyboard Interrupt Module (KBI 151 Chapter 13 Computer Operating Properly (COP 157 Chapter 14 Low-Voltage Inhibit (LVI 161 Chapter 15 Central Processor Unit (CPU 165 Chapter 16 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Chapter 18 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 213 Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev ...
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... List of Chapters 6 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2.2 Clock Start-up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Freescale Semiconductor Chapter 1 General Description Chapter 2 Memory Chapter 3 Configuration Register (CONFIG) Chapter 4 System Integration Module (SIM) MC68HC908LV8 Data Sheet, Rev ...
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... Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.8 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3.9 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.4.1 Crystal Amplifier Input Pin (OSC1 5.4.2 Crystal Amplifier Output Pin (OSC2 Chapter 5 Clock Generator Module (CGM) MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.7 TIM During Break Interrupts 6.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Freescale Semiconductor ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 DDA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SSA Chapter 6 Timer Interface Module (TIM) MC68HC908LV8 Data Sheet, Rev ...
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... Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.7.1 ADC10 Analog Power Pin (V 8.7.2 ADC10 Analog Ground Pin (V 8.7.3 ADC10 Voltage Reference High Pin (V 8.7.4 ADC10 Voltage Reference Low Pin (VREFL 109 10 Chapter 7 Chapter 8 Analog-to-Digital Converter (ADC 108 DDA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SSA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 REFH MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Port C Data Register (PTC 141 10.4.2 Data Direction Register C (DDRC 141 10.5 Port 142 10.5.1 Port D Data Register (PTD 142 10.5.2 Data Direction Register D (DDRD 143 Freescale Semiconductor Chapter 9 Liquid Crystal Display (LCD) Driver , 119 LCD1 LCD2 LCD3 Chapter 10 Input/Output (I/O) Ports MC68HC908LV8 Data Sheet, Rev ...
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... COPRS (COP Rate Select 159 13.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12 Chapter 11 External Interrupt (IRQ) Chapter 12 Keyboard Interrupt Module (KBI) Chapter 13 Computer Operating Properly (COP) MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.2.2 Break Module Registers 179 16.2.2.1 Break Status and Control Register (BRKSCR 179 16.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.2.2.3 Break Status Register 180 Freescale Semiconductor Chapter 14 Low-Voltage Inhibit (LVI) Chapter 15 Central Processor Unit (CPU) Chapter 16 Development Support MC68HC908LV8 Data Sheet, Rev ...
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... ADC10 Characteristics 208 17.11 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 17.11.1 CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 17.11.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 17.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Ordering Information and Mechanical Specifications 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 18.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 14 Chapter 17 Electrical Specifications Chapter 18 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... General Description 1.1 Introduction The MC68HC908LV8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types. ...
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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • • Fast 16/8 divide instruction • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908LV8. 16 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... ANALOG-TO-DIGITAL CONVERTER MODULE LIQUID CRYSTAL DISPLAY DRIVER MODULE * Pin contains integrated pullup device. ** Pin contains integrated pullup device if configured as KBI. † High current sink pin, 15mA. MC68HC908LV8 Data Sheet, Rev. 2 MCU Block Diagram PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 PTA3/KBI3** PTA2/KBI2** ...
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... PTE1/FP4 5 PTE2/FP5 6 PTE3/FP6 7 PTE4/FP7 8 PTE5/FP8 9 PTE6/FP9 10 PTE7/FP10 11 PTD0/FP11 12 PTD1/FP12 13 Figure 1-2. 52-Pin LQFP Pin Assignment 1.5 Pin Functions Description of the pin functions are provided in 18 Table 1-1. MC68HC908LV8 Data Sheet, Rev. 2 PTB5/T2CH1 39 PTB4/T2CH0 38 PTA7/ADC3 37 PTA6/ADC2 36 PTA5/ADC1 35 PTA4/ADC0 34 PTA3/KBI3 33 PTA2/KBI2 32 PTA1/KBI1 31 PTA0/KBI0 30 PTC7 29 PTC6 28 PTC5/FP24 ...
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... PTB3 as T1CH1 of TIM1 PTB5/T2CH1 PTB6/FP1 PTB4 as T2CH0 of TIM2 PTB7/FP2 PTB5 as T2CH1 of TIM2 PTB6–PTB7 as LCD frontplane drivers, FP1–FP2 Freescale Semiconductor Table 1-1. Pin Functions Pin Description MC68HC908LV8 Data Sheet, Rev. 2 Pin Functions Voltage Input/Output Level Input Output 0V V Input ...
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... PTD5/FP16 PTD6/FP17 PTD7/FP18 PTE0/FP3 8-bit general-purpose I/O port PTE1/FP4 PTE2/FP5 PTE3/FP6 PTE4/FP7 PTE0–PTE7 as LCD frontplane drivers, FP3–FP10 PTE5/FP8 PTE6/FP9 PTE7/FP10 20 Table 1-1. Pin Functions (Continued) Pin Description MC68HC908LV8 Data Sheet, Rev. 2 Voltage Input/Output Level V Input/output DD V Output DD V Input/output DD V Output DD ...
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... COP control register, COPCTL 2.3 Monitor ROM The 350 bytes at addresses $FE20–$FF7D are reserved ROM addresses that contain the instructions for the monitor functions. Freescale Semiconductor Figure 2-2, contain most of the control, status, and data registers. MC68HC908LV8 Data Sheet, Rev. 2 Figure 2-1, includes: 21 ...
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... BREAK ADDRESS LOW REGISTER (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 16 BYTES MONITOR ROM 350 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) MONITOR JUMP TABLE 24 BYTES UNIMPLEMENTED 57 BYTES USER FLASH VECTORS 48 BYTES Figure 2-1. Memory Map MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... DDRD5 DDRD4 DDRE7 DDRE6 DDRE5 DDRE4 PTE7 PTE6 PTE5 PTE4 Unaffected by reset X = Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Monitor ROM Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 PTC3 PTC2 PTC1 PTC0 PTD3 PTD2 PTD1 ...
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... LVIRSTD LVIPWRD ( TOF 0 TOIE TSTOP 0 TRST Bit Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev Bit 0 PPI1CLKS PPI1CLKS HDB3 HDB2 KEYF 0 IMASKK MODEK ACKK KBIE3 KBIE2 KBIE1 KBIE0 ...
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... Indeterminate after reset Bit Indeterminate after reset TOF 0 TOIE TSTOP 0 TRST Bit Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Monitor ROM Bit Bit Bit Bit 0 ...
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... Indeterminate after reset Bit Indeterminate after reset PLLF PLLIE PLLON BCS LOCK 0 AUTO ACQ Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev Bit Bit Bit Bit 0 ...
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... ADLPC ADIV1 ADIV0 ADICLK FCCTL1 FCCTL0 DUTY1 Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Monitor ROM Bit 0 MUL11 MUL10 MUL9 MUL8 MUL3 MUL2 MUL1 MUL0 VRS3 VRS2 VRS1 VRS0 ...
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... F15B1 F15B0 F17B3 F17B2 F17B1 F17B0 F19B3 F19B2 F19B1 F19B0 Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev Bit 0 LCCON3 LCCON2 LCCON1 LCCON0 F0B3 F0B2 F0B1 F0B0 F2B3 F2B2 F2B1 F2B0 ...
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... R 0 IF6 IF5 IF4 IF3 Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Monitor ROM Bit 0 F20B3 F20B2 F20B1 F20B0 F22B3 F22B2 F22B1 F22B0 F24B3 F24B2 F24B1 F24B0 U U ...
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... LVIIF 0 LVIIE LVIIAK BPR7 BPR6 BPR5 BPR4 Unaffected by reset; $FF when blank Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset X = Indeterminate = Unimplemented MC68HC908LV8 Data Sheet, Rev Bit 0 0 IF17 IF16 ...
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... IF6 TIM1 overflow $FFF1 $FFF2 IF5 TIM1 channel 1 $FFF3 $FFF4 IF4 TIM1 channel 0 $FFF5 $FFF6 IF3 PLL $FFF7 $FFF8 IF2 LVI $FFF9 $FFFA IF1 IRQ $FFFB $FFFC — SWI $FFFD $FFFE — Reset $FFFF MC68HC908LV8 Data Sheet, Rev. 2 Monitor ROM Vector 31 ...
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... Programming tools are available from Freescale Semiconductor. Contact your local representative for more information. A security feature prevents viewing of the FLASH contents security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 32 NOTE NOTE NOTE NOTE MC68HC908LV8 Data Sheet, Rev. 2 (1) Freescale Semiconductor ...
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... Program operation selected 0 = Program operation not selected Freescale Semiconductor HVEN MC68HC908LV8 Data Sheet, Rev. 2 FLASH Control Register 2 1 Bit 0 MASS ERASE PGM ...
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... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 34 NOTE NOTE NOTE (FLBPR does not equal $FF). NOTE MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... FLASH memory; the code must be executed from RAM. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. Do not exceed t maximum. prog Freescale Semiconductor NOTE NOTE NOTE MC68HC908LV8 Data Sheet, Rev. 2 FLASH Control Register 35 ...
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... Write data to the FLASH address to be programmed 8 Wait for a time, t prog Completed programming this row MC68HC908LV8 Data Sheet, Rev Clear PGM bit Wait for a time, t nvh Clear HVEN bit Wait for a time, t rcv End of Programming Freescale Semiconductor ...
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... Freescale Semiconductor NOTE Register. Once the FLBPR is programmed with a value other than BPR6 BPR5 BPR4 BPR3 Unaffected by reset; $FF when blank 16-bit memory address 1 1 BPR[7:0] MC68HC908LV8 Data Sheet, Rev. 2 FLASH Protection 2 1 Bit 0 BPR2 BPR1 BPR0 ...
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... The entire FLASH memory is not protected. MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Freescale Semiconductor – –2 CGMXCLK cycles) Bit STOP_ R PEE XCLKEN COPRS LVISTOP LVIRSTD LVIPWRD Reserved MC68HC908LV8 Data Sheet, Rev PDE PCEH PCEL LVISEL1 ( SSREC STOP ( Bit 0 LVISEL0 (2) 1 COPD ...
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... LVI module reset disabled 0 = LVI module reset enabled 40 NOTE LVISTOP LVIRSTD LVIPWRD Reserved U = Unaffected 13 4 – CGMXCLK cycles 18 4 – CGMXCLK cycles MC68HC908LV8 Data Sheet, Rev. 2 Figure 3-2 and 2 1 Bit 0 SSREC STOP COPD Freescale Semiconductor ...
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... PTE0/FP3–PTE7/FP10 pins configured as LCD frontplane driver pins: FP3–FP10 0 = PTE0/FP3–PTE7/FP10 pins configured as standard I/O pins: PTE0–PTE7 Freescale Semiconductor NOTE PEE PDE PCEH Reserved U = Unaffected MC68HC908LV8 Data Sheet, Rev. 2 Configuration Register 2 (CONFIG2 Bit 0 PCEL LVISEL1 LVISEL0 ...
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... LVI module will come into action. LVISEL1 and DD Table 3-1. Trip Voltage Selection LVISEL0 Comments 0 0 For For Chapter 17 Electrical Specifications for full parameters. MC68HC908LV8 Data Sheet, Rev. 2 (1) Reserved = 3 V operation = 5 V operation Reserved Freescale Semiconductor ...
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... PLL-based or oscillator-based clock output from CGM module CGMOUT (Bus clock = CGMOUT ÷ 2) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal Freescale Semiconductor Table 4-1. Signal Name Conventions Description MC68HC908LV8 Data Sheet, Rev ...
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... BCFE Figure 4-2. SIM I/O Register Summary MC68HC908LV8 Data Sheet, Rev. 2 MODULE STOP MODULE WAIT CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM, OSC) COP CLOCK CGMXCLK (FROM OSC) CGMOUT (FROM CGM) INTERNAL CLOCKS LVI (FROM LVI MODULE) ...
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... Unimplemented CGMXCLK SIM COUNTER SYSTEM INTEGRATION MODULE CGMOUT SIMDIV2 Figure 4-3. CGM Clock Signals MC68HC908LV8 Data Sheet, Rev. 2 SIM Bus Clock Control and Generation IF2 IF1 IF9 IF8 ...
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... Reset Type POR/LVI All others 46 4.6.2 Stop 4.4 SIM Counter), but an external reset does not. Each of shows the relative timing. Table 4-2. PIN Bit Set Timing Number of Cycles Required to Set PIN 4163 (4096 + ( MC68HC908LV8 Data Sheet, Rev. 2 Mode.) 4.7 SIM Registers.) Freescale Semiconductor ...
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... Freescale Semiconductor Figure 4-4. External Reset Timing NOTE RST PULLED LOW BY MCU 32 CYCLES Figure 4-5. Internal Reset Timing ILLEGAL OPCODE RST COPRST INTERNAL RESET LVI POR Figure 4-6. Sources of Internal Reset MC68HC908LV8 Data Sheet, Rev. 2 Reset and System Initialization VECT H VECT L Figure 4-5. 32 CYCLES VECTOR HIGH 47 ...
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... The SIM actively pulls down the RST pin for all internal reset sources CYCLES CYCLES Figure 4-7. POR Recovery on the RST pin disables the COP module. TST MC68HC908LV8 Data Sheet, Rev. 2 $FFFE $FFFF while the MCU is in monitor TST Freescale Semiconductor ...
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... External reset has no effect on the SIM counter. free-running after all reset states. (See internal reset recovery sequences.) Freescale Semiconductor (See 4.6.2 Stop Mode 4.3.2 Active Resets from Internal Sources MC68HC908LV8 Data Sheet, Rev. 2 SIM Counter voltage falls to the DD Chapter 16 Development Support.) for details.) The SIM counter is ...
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... SP – – 1[7:0] PC – 1[15: Figure 4-8 Interrupt Entry Timing SP – – – 1 CCR – 1[15:8] PC – 1[7:0] Figure 4-9. Interrupt Recovery Timing MC68HC908LV8 Data Sheet, Rev. 2 Figure 4-8 shows VECT H VECT L START ADDR CCR V DATA H V DATA L OPCODE OPCODE OPERAND ...
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... I BIT SET? YES INTERRUPT? NO I-BIT SET? NO IRQ YES INTERRUPT? NO STACK CPU REGISTERS SET I-BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION? NO EXECUTE INSTRUCTION Figure 4-10. Interrupt Processing MC68HC908LV8 Data Sheet, Rev. 2 Exception Control 51 ...
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... CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI . Interrupt Recognition Example NOTE NOTE MC68HC908LV8 Data Sheet, Rev. 2 BACKGROUND ROUTINE Freescale Semiconductor ...
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... MC68HC908LV8 Data Sheet, Rev. 2 Exception Control 2 1 Bit 0 IF1 Table 2- Bit 0 IF9 IF8 IF7 Table 2- Bit 0 ...
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... SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. 54 Support.) The SIM puts the CPU into the break MC68HC908LV8 Data Sheet, Rev. 2 Figure 4-15 shows Freescale Semiconductor ...
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... Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 4-15. Wait Mode Entry Timing $6E0B $6E0C $00FF $A6 $A6 $01 $ CYCLES CYCLES $6E0B $A6 $A6 NOTE MC68HC908LV8 Data Sheet, Rev. 2 Low-Power Modes SAME SAME SAME $00FE $00FD $00FC $6E RST VCT H RST VCT L 55 ...
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... Figure 4-18 NOTE STOP ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 4-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 MC68HC908LV8 Data Sheet, Rev. 2 shows stop mode entry timing. SAME SAME SAME SP SP – – – 3 Freescale Semiconductor ...
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... RETURNLO is not zero, ;then just decrement low byte. ;Else deal with high byte, too. ;Point to WAIT/STOP opcode. ;Restore H register PIN COP ILOP ILAD MC68HC908LV8 Data Sheet, Rev. 2 SIM Registers 2 1 Bit 0 SBSW R R (1) Note Bit 0 0 LVI 0 ...
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... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908LV8 Data Sheet, Rev Bit Freescale Semiconductor ...
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... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 5-1 shows the structure of the CGM. Figure 5 summary of the CGM registers. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev ...
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... PLL ANALOG AUTOMATIC INTERRUPT MODE CONTROL CONTROL AUTO ACQ PLLIE PLLF PRE1–PRE0 P 2 FREQUENCY DIVIDER Figure 5-1. CGM Block Diagram MC68HC908LV8 Data Sheet, Rev. 2 CGMXCLK (TO: SIM, LCD, COP) A CGMOUT CLOCK ÷ (TO SIM) SELECT CIRCUIT SIMDIV2 *WHEN (FROM SIM) CGMOUT = B E ...
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... MUL7 MUL6 MUL5 VRS7 VRS6 VRS5 Unimplemented Figure 5-2. CGM I/O Register Summary MC68HC908LV8 Data Sheet, Rev. 2 Functional Description BCS PRE1 PRE0 VPR1 MUL11 MUL10 MUL9 0 0 ...
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... The circuit determines the mode of the PLL and the lock condition based on RDV this comparison. 62 VRS , (38.4 kHz) times a linear factor, L, and a power-of-two factor VCLK Modes. The value of the external capacitor and the MC68HC908LV8 Data Sheet, Rev Modulating the voltage on the is equal to the nominal VRS RCLK , is fed back through a programmable /(N × ...
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... ACQ bit must be clear. Freescale Semiconductor 5.5.2 PLL Bandwidth Control 5.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes.) 5.8 Acquisition/Lock Time Specifications 5.8 Acquisition/Lock Time Specifications Register.) MC68HC908LV8 Data Sheet, Rev. 2 Functional Description Register.) 5.5.2 PLL 5.3.8 Base Clock Selector Circuit.) 5.6 for for 63 ...
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... MAX ⎝ f ⎠ ⎩ RCLK MC68HC908LV8 Data Sheet, Rev. 2 (See 5.8 ACQ , and the reference clock divider, R. /R. For stability and lock time reduction RCLK to a value determined RCLK Section 23. Electrical to an integer divisor of f RCLK BUSDES ⎛ ...
Page 65
... VCLK 19,660,800 ≤ f < 39,321,600 VCLK = 38.4 kHz NOM ⎛ ⎞ f VCLK ⎜ ⎟ round -------------------------- ⎝ E ⎠ × NOM MC68HC908LV8 Data Sheet, Rev. 2 Functional Description ⎞ ⎟ ⎠ ⎞ ⎟ ⎠ and f . VCLK BUS ...
Page 66
... MC68HC908LV8 Data Sheet, Rev. 2 VRS and f . For proper VRS VCLKDES , and f must be as close VCLKDES VRS ...
Page 67
... Care should be taken with PCB routing in order to minimize signal cross talk and noise. (See CGM Electrical Specifications for capacitor and resistor values.) Freescale Semiconductor 5.3.6 Programming the PLL Circuit.) MC68HC908LV8 Data Sheet, Rev. 2 Functional Description does not account for three possible Figure 17.11.2 5-3. ...
Page 68
... PLL. Connect the V DDA potential as the V pin CGMXCLK OSC2 CGMXFC 10 kΩ 0.01 µF RS 0.033 µF C2 5-3.) NOTE ) DDA MC68HC908LV8 Data Sheet, Rev SSA DDA V DD CBYP 0.1 µF pin to the same voltage DDA Freescale Semiconductor ...
Page 69
... PLL VCO Range Select • PLL reference divider select register (PMDS) (See 5.5.5 PLL Reference Divider Select Freescale Semiconductor NOTE ) SSA NOTE is physically bonded to the V SSA Register.) Registers.) Register.) Register.) MC68HC908LV8 Data Sheet, Rev. 2 CGM Registers pin to the same voltage SSA pin ...
Page 70
... CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT PLLF PLLON BCS PRE1 Unimplemented Figure 5-4. PLL Control Register (PCTL) NOTE MC68HC908LV8 Data Sheet, Rev Bit 0 PRE0 VPR1 VPR0 5.3.8 Base Clock Selector 5.3.8 Base Clock Selector Circuit.) Reset Freescale Semiconductor ...
Page 71
... PLL.) PRE1 and PRE0 cannot be written when the 5.3.6 Programming the PLL, and VRS MC68HC908LV8 Data Sheet, Rev. 2 CGM Registers Prescaler Multiplier 5.5.4 PLL VCO Range Select . VPR1:VPR0 cannot be written when VCO Power-of-Two Range Multiplier ...
Page 72
... Reset clears this bit, enabling acquisition mode Tracking mode 0 = Acquisition mode LOCK 0 0 ACQ Unimplemented R MC68HC908LV8 Data Sheet, Rev Bit Reserved Freescale Semiconductor ...
Page 73
... VRS6 VRS5 VRS4 VRS3 PLL, and . VRS[7:0] cannot be written when the PLLON bit in the VRS Exceptions.) A value of $00 in the VCO range select MC68HC908LV8 Data Sheet, Rev. 2 CGM Registers 2 1 Bit 0 MUL10 MUL9 MUL8 Bit 0 MUL2 MUL1 ...
Page 74
... Exceptions.). Reset initializes the register to $40 NOTE RDS3 Unimplemented PLL.) RDS[3:0] cannot be written when the PLLON 5.3.7 Special Programming NOTE NOTE MC68HC908LV8 Data Sheet, Rev. 2 5.3.8 Base 2 1 Bit 0 RDS2 RDS1 RDS0 Exceptions.) Reset initializes the Freescale Semiconductor ...
Page 75
... To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit. Freescale Semiconductor NOTE 4.7.3 SIM Break Flag Control MC68HC908LV8 Data Sheet, Rev. 2 Special Modes Register.) 75 ...
Page 76
... Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. 76 5.3.3 PLL Circuits, Register.) 5.8.3 Choosing a . The power supply potential alters the DDA MC68HC908LV8 Data Sheet, Rev. 2 RDV and the XCLK 5.3.6 Programming the PLL, and Filter.) Freescale Semiconductor . ...
Page 77
... Freescale Semiconductor Time, the external filter network is critical to the is recommended when using a 32.768kHz reference clock CGMXFC 10 kΩ 0.01 µF V SSA (a) Figure 5-10. PLL Filter MC68HC908LV8 Data Sheet, Rev. 2 Acquisition/Lock Time Specifications Figure 5-10 (b) is used in CGMXFC 0.47 µF V SSA (b) 77 ...
Page 78
... Clock Generator Module (CGM) 78 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 79
... For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1. Freescale Semiconductor Table 6-1. Pin Name Conventions T[1,2]CH0 TIM1 PTB2/T1CH0/PPIECK TIM2 PTB4/T2CH0 NOTE MC68HC908LV8 Data Sheet, Rev. 2 Figure 6-1 is Table 6-1. T[1,2]CH1 PTB3/T1CH1 PTB5/T2CH1 79 ...
Page 80
... T1SC and T2SC. 80 PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A MS0B ELS0B ELS0A CH1F MS0A Figure 6-1. TIM Block Diagram NOTE MC68HC908LV8 Data Sheet, Rev. 2 TOF INTERRUPT LOGIC TOIE TOV0 PORT CH0MAX T[1,2]CH0 LOGIC INTERRUPT LOGIC CH0IE TOV1 PORT CH1MAX T[1,2]CH1 ...
Page 81
... Bit Bit Bit Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Functional Description Bit 0 0 PS2 PS1 PS0 Bit Bit ...
Page 82
... Indeterminate after reset CH1F 0 CH1IE MS1A Bit Indeterminate after reset Bit Indeterminate after reset = Unimplemented MC68HC908LV8 Data Sheet, Rev Bit Bit ELS0B ELS0A TOV0 CH0MAX ...
Page 83
... PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing Freescale Semiconductor NOTE MC68HC908LV8 Data Sheet, Rev. 2 Functional Description 83 ...
Page 84
... Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 84 6.9.1 TIM Status and Control OVERFLOW PERIOD OUTPUT OUTPUT COMPARE COMPARE NOTE MC68HC908LV8 Data Sheet, Rev. 2 Register. OVERFLOW OUTPUT COMPARE 6.4.4 Pulse Width Freescale Semiconductor ...
Page 85
... PWM signal generation when changing the PWM pulse width to a new, much larger value the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Freescale Semiconductor NOTE Table 6-3.) NOTE MC68HC908LV8 Data Sheet, Rev. 2 Functional Description Table 6-3.) 85 ...
Page 86
... The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. (See 86 Registers.) 21.5.4 SIM Break Flag Control MC68HC908LV8 Data Sheet, Rev. 2 Register.) Freescale Semiconductor ...
Page 87
... Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: TOF Write: 0 Reset: 0 Figure 6-4. TIM Status and Control Register (TSC) Freescale Semiconductor Conventions. NOTE TOIE TSTOP TRST Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 I/O Signals 2 1 Bit 0 PS2 PS1 PS0 ...
Page 88
... Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Internal bus clock ÷ Not available MC68HC908LV8 Data Sheet, Rev. 2 Table Freescale Semiconductor ...
Page 89
... NOTE MC68HC908LV8 Data Sheet, Rev. 2 I/O Registers 2 1 Bit Bit Bit Bit Bit Bit Bit 0 ...
Page 90
... TIM2 channel 0 status and control registers CH0IE MS0B MS0A ELS0B CH1IE MS1A ELS1B MC68HC908LV8 Data Sheet, Rev Bit 0 ELS0A TOV0 CH0MAX Bit 0 ELS1A TOV1 CH1MAX Freescale Semiconductor ...
Page 91
... Toggle output on compare Buffered output 10 compare or Clear output on compare buffered PWM 11 MC68HC908LV8 Data Sheet, Rev. 2 I/O Registers Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising or falling edge Set output on compare ...
Page 92
... In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written. 92 NOTE NOTE Figure 6-11 shows, the CHxMAX bit takes effect in the cycle OVERFLOW OVERFLOW OVERFLOW OUTPUT OUTPUT COMPARE COMPARE Figure 6-11. CHxMAX Latency MC68HC908LV8 Data Sheet, Rev. 2 OVERFLOW OUTPUT COMPARE Freescale Semiconductor ...
Page 93
... Indeterminate after reset Indeterminate after reset Indeterminate after reset MC68HC908LV8 Data Sheet, Rev. 2 I/O Registers 2 1 Bit Bit Bit Bit Bit Bit Bit Bit 0 ...
Page 94
... Timer Interface Module (TIM) 94 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 95
... The latch can be cleared by writing to the ACKK bit in the KBSCR register. The PPI counter can count and generate interrupts even when the MCU is in stop mode if the corresponding clock source is enabled. Figure 7 block diagram of the PPI. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev ...
Page 96
... Figure 7-2. Port B High Current Drive Control Register (HDB COUNTER CLK OV CLR SEL RESET ACKK PPI1L HDB5 HDB4 HDB3 MC68HC908LV8 Data Sheet, Rev PPI1L PPI1IREQ R To KBI Interrupt logic PPI1IE2 PPI1IE1 PPI1IE0 Bit 0 HDB2 PPI1CLKS1 PPI1CLKS0 0 0 ...
Page 97
... Interrupt Period PPI and its associated interrupts are disabled 512 PPI counts 1,024 PPI counts 2,048 PPI counts 4,096 PPI counts 8,192 PPI counts 16,384 PPI counts 32,768 PPI counts MC68HC908LV8 Data Sheet, Rev. 2 PPI I/O Registers 2 1 Bit 0 KBIE2 KBIE1 KBIE0 0 ...
Page 98
... The code below shows an example of a system having PPI and KBI3 enabled, with each running from a different asynchronous clock source. 98 (KBI).) KEYF Unimplemented (KBI).) (KBI).) Register.) MC68HC908LV8 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Freescale Semiconductor ...
Page 99
... BSET ACKK,ACKK_R KBI_ISR_X: RTI Freescale Semiconductor ; MODEK = ENABLE KBI INT ; ENABLE ALL INT ; PUT MCU IN STOP ; WAIT KBI3 ; ENABLE WHEN HIGH ; LOOP AGAIN ; DISABLE KBI3 ; DO KBI3 SERVICES HERE ; DO PPI1 SERVICES HERE ; CLEAR ALL FLAGS MC68HC908LV8 Data Sheet, Rev. 2 Using the PPI 99 ...
Page 100
... Programmable Periodic Interrupt (PPI) 100 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 101
... AIEN ADCO ADCH4 AD7 AD6 AD5 ADLPC ADIV1 ADIV0 ADICLK Figure 8-1. ADC I/O Register Summary MC68HC908LV8 Data Sheet, Rev ADCH3 ADCH2 ADCH1 0/AD9 Reserved AD4 AD3 AD2 AD1 Reserved ...
Page 102
... ADCLK ADCK CLOCK CONTROL SEQUENCER DIVIDE SAR CONVERTER DATA REGISTERS ADRH:ADRL Figure 8-2. ADC10 Block Diagram REFL and V are straight-line linear conversions. REFL NOTE MC68HC908LV8 Data Sheet, Rev. 2 ASYNC ACLKEN CLOCK GENERATOR ACLK BUS CLOCK ALTERNATE CLOCK SOURCE 1 AIEN INTERRUPT 2 COCO and V ...
Page 103
... A conversion is completed when the result of the conversion is transferred into the data result registers, ADRH and ADRL. This is indicated by the setting of the COCO bit. An interrupt is generated if AIEN is high at the time that COCO is set. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Functional Description Table 8-1 to determine source and ...
Page 104
... X Bus ADCK 0 1 ≥ Bus ADCK MC68HC908LV8 Data Sheet, Rev. 2 Table 8-1. Maximum Conversion Time 18 ADCK + 3 bus clock 18 ADCK + 3 bus clock + 5 µs 16 ADCK 38 ADCK + 3 bus clock 38 ADCK + 3 bus clock + 5 µs 36 ADCK 21 ADCK + 3 bus clock 21 ADCK + 3 bus clock + 5 µs 19 ADCK 41 ADCK + 3 bus clock 41 ADCK + 3 bus clock + 5 µ ...
Page 105
... NOTE minimum and f ADCK lower than (if available). REFH REFL to V (if available). DDA SSA at a quiet point in the ground plane. SS MC68HC908LV8 Data Sheet, Rev. 2 Functional Description = 11.25 µs 4 MHz ADCK ) is kept below high (4096*I ) for less than ADVIN Leak 105 ...
Page 106
... LSB REFH REFL 10-bit mode consequence, LSB LSB ). Note, if the last conversion is $3FE, then the LSB MC68HC908LV8 Data Sheet, Rev (if available). This will SSA , one-time error. LSB and the code width of the last ($FF ). Note, if the first LSB LSB ) is used ...
Page 107
... ADCO in the ADC10 status and Control Register before executing the STOP instruction. In single conversion mode the ADC10 automatically enters a low-power state when the conversion is complete not necessary to set the channel select bits (ADCH[4:0]) to all 1s to enter a low-power state. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Interrupts 107 ...
Page 108
... This should be the only ground connection between SSA pin makes a good single point ground location. SSA ) REFH . If externally available, V DDA ). DDA MC68HC908LV8 Data Sheet, Rev connected internally DDA . External filtering DD is connected internally SSA . SS may be connected to the same REFH ...
Page 109
... V REFL AIEN ADCO ADCH4 ADCH3 MC68HC908LV8 Data Sheet, Rev. 2 loop. The best external component REFL pin to the same voltage REFL when the sampling capacitor is REFL at the single point SSA 2 1 Bit 0 ADCH2 ADCH1 ...
Page 110
... I/O pad. Terminating continuous convert mode this way will prevent an additional, single conversion from being performed not necessary to set the channel select bits to all 1s to place the ADC10 in a low-power state, however, because the module is automatically placed in a low-power state when a conversion completes. 110 Table 8-2. MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 111
... Reserved MC68HC908LV8 Data Sheet, Rev. 2 (1) (2) Input Select 0 AD0 1 AD1 0 AD2 1 AD3 0 AD4 1 AD5 0 Unused Unused 1 Unused (3) 0 BANDGAP REF 1 Reserved 0 Reserved V 1 REFH V 0 REFL ...
Page 112
... ADIV1 ADIV0 ADICLK MODE1 Table 8-3. ADC10 Clock Divide Ratio ADIV0 Divide Ratio (ADIV MC68HC908LV8 Data Sheet, Rev Bit 0 AD2 AD1 AD0 Bit 0 MODE0 ADLSMP ACLKEN Clock Rate Input clock ÷ ...
Page 113
... The ADICLK bit specifies the input clock source and conversions will not continue in stop mode Freescale Semiconductor Table 8-4. Mode Selection Mode 8-bit, right-justified, ADCSC write-triggered mode enabled 10-bit, right-justified, ADCSC write-triggered mode enabled Reserved. Reserved. MC68HC908LV8 Data Sheet, Rev. 2 Registers 113 ...
Page 114
... Analog-to-Digital Converter (ADC) 114 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 115
... The generic pin names appear in the text Table 9-1. Pin Name Conventions Full MCU Pin Name FP0/BP3 BP0–BP2 PTB6/FP1–PTB7/FP2 PTE0/FP3–PTE7/FP10 PTD0/FP11–PTD7/FP18 PTC0/FP19–PTC5/FP24 MC68HC908LV8 Data Sheet, Rev. 2 Pin Selected for LCD Function by: — — LCDE in LCDCR PEE in CONFIG2 LCDE in LCDCR PDE in CONFIG2 LCDE in LCDCR ...
Page 116
... U U F21B3 F21B2 F21B1 F21B0 F23B3 F23B2 F23B1 F23B0 Unaffected = Unimplemented Figure 9-1. LCD I/O Register Summary MC68HC908LV8 Data Sheet, Rev DUTY0 LCLK2 LCLK1 LCCON3 LCCON2 LCCON1 F1B0 F0B3 F0B2 F0B1 U ...
Page 117
... The resistor ladder is disconnected from V DD PORT-E LOGIC PORT-D LOGIC LCD FRONTPLANE DRIVER AND DATA LATCH LCDE (LCDCR) STATE CONTROL 1/1 1/3 1/4 Figure 9-2. LCD Block Diagram MC68HC908LV8 Data Sheet, Rev. 2 Functional Description Figure 9-3 shows a simplified schematic pin. Voltages LCD to reduce DD PTC0/FP19 PTC1/FP20 PTC2/FP21 PTC3/FP22 ...
Page 118
... When the LCD driver module is enabled the backplane waveforms for the selected duty are driven out of the backplane pins. The backplane waveforms are periodic and are shown are shown in Figure 9-6, and Figure 9-7. 118 LCD FP1 FP24 LCCON[3:0] MC68HC908LV8 Data Sheet, Rev. 2 BP0 BP1 BP2 Figure Freescale Semiconductor 9-5, ...
Page 119
... LCD ) bias ) bias Chapter 5 Clock Generator Module LCD WAVEFORM BASE CLOCK × DUTY 1 256 × (1/3) = 11.72 ms Figure 9-3), R value to 146kΩ. LCD MC68HC908LV8 Data Sheet, Rev. 2 Functional Description . and V are internal DD LCD1 LCD2 LCD3 using a resistor ladder (see LCD (CGM)) as the input 1 ...
Page 120
... To further reduce power consumption, the LCD module should be powered-down by clearing the LCDE bit before executing the STOP instruction. 120 HIGH CURRENT SELECTED BEFORE SWITCHING EDGE, PERIOD IS DEFINED BY FCCTL[1:0] Figure 9-4. Fast Charge Timing . The relative voltages, V LCD3 MC68HC908LV8 Data Sheet, Rev. 2 and V , are altered LCD1 LCD2 – V LCD LCD3 ...
Page 121
... BP0 BP1 BP2 NOTES: 1. BP3 is not used 1/3 duty, 1FRAME has three times the cycle of LCD waveform base clock. Figure 9-6. 1/3 Duty LCD Backplane Driver Waveforms Freescale Semiconductor Figure 1FRAME 1FRAME MC68HC908LV8 Data Sheet, Rev. 2 I/O Signals 9-5, Figure 9-6, and Figure 9-7 V LCD V LCD1 V LCD2 ...
Page 122
... DATA LATCH ON OFF FxB0 — — — 0 FxB0 — — — 1 Figure 9-8. Static LCD Frontplane Driver Waveforms 122 1FRAME and Figure 9-11 appear on the frontplane pins. FPx OUTPUT 1FRAME MC68HC908LV8 Data Sheet, Rev LCD V LCD1 V LCD2 V LCD3 V LCD V LCD1 V LCD2 V LCD3 V LCD ...
Page 123
... FxB1 FxB0 — FxB2 FxB1 FxB0 — FxB2 FxB1 FxB0 — Figure 9-9. 1/3 Duty LCD Frontplane Driver Waveforms Freescale Semiconductor FPx OUTPUT 1FRAME MC68HC908LV8 Data Sheet, Rev. 2 I/O Signals V LCD V LCD1 V LCD2 V LCD3 V LCD V LCD1 V LCD2 V LCD3 V LCD V LCD1 V LCD2 ...
Page 124
... FxB3 FxB2 FxB1 FxB0 FxB3 FxB2 FxB1 FxB0 FxB3 FxB2 FxB1 FxB0 Figure 9-10. 1/4 Duty LCD Frontplane Driver Waveforms 124 FPx OUTPUT 1FRAME MC68HC908LV8 Data Sheet, Rev LCD V LCD1 V LCD2 V LCD3 Freescale Semiconductor ...
Page 125
... FxB3 FxB2 FxB1 FxB0 FxB3 FxB2 FxB1 FxB0 FxB3 FxB2 FxB1 FxB0 Figure 9-11. 1/4 Duty LCD Frontplane Driver Waveforms (continued) Freescale Semiconductor FPx OUTPUT 1FRAME MC68HC908LV8 Data Sheet, Rev. 2 I/O Signals V LCD V LCD1 V LCD2 V LCD3 125 ...
Page 126
... FP1 FP0 F3B1 F3B0 F2B3 F2B2 — — — — FP2 MC68HC908LV8 Data Sheet, Rev. 2 BP0 (a, b COMMONED) BP1 ( COMMONED) BP2 (d, e COMMONED) F0B1 F0B0 f — F2B1 F2B0 ...
Page 127
... As shown in the waveform, the voltage peaks reach the LCD-ON voltage, V the segment will be ON. BP1–FP0 Figure 9-14. "f" Segment Voltage Waveform Freescale Semiconductor 1FRAME BP0 BP1 BP2 FP0 FP1 FP2 MC68HC908LV8 Data Sheet, Rev. 2 Seven Segment Display Connection V LCD V LCD1 V LCD2 V LCD3 V LCD ...
Page 128
... These read/write bits are used to select the value of the resistors in resistor ladder for LCD voltages. Reset clears the FC and LC bits. 128 LCCON3 Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 LCD +V LCD +V LCD1 +V LCD2 0 –V LCD2 –V LCD1 –V LCD 2 ...
Page 129
... This voltage controls the contrast of the LCD. bias Table 9-3. LCD Bias Voltage Control LCCON1 LCCON0 MC68HC908LV8 Data Sheet, Rev. 2 I/O Registers Bias Voltage (approximate % 0.6 2.9 5.2 7.4 9.6 11.6 13.5 15.3 17.2 18.8 20.5 22.0 23.6 25.0 26.4 27.7 129 ...
Page 130
... LCDCLK/128. Not used Table 9-5. LCD Duty Cycle Selection Description Static selected; FP0/BP3 pin function as FP0. 1/3 duty cycle selected; FP0/BP3 pin functions as FP0. 1/4 duty cycle selected; FP0/BP3 pin functions as BP3. Not used MC68HC908LV8 Data Sheet, Rev Bit 0 LCLK2 LCLK1 LCLK0 0 ...
Page 131
... F7B3 F7B2 F7B1 F9B3 F9B2 F9B1 F11B3 F11B2 F11B1 F13B3 F13B2 F13B1 Unaffected = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 I/O Registers LCD Frame Rate LCD Frame Rate ( XTAL XTAL 4.9152MHz 32.768kHz 1/3 duty 1/4 duty 1/3 duty 85.3 64 — 42.7 32 — 21.3 16 — 10.7 8 — ...
Page 132
... F21B3 F21B2 F21B1 F21B0 F23B3 F23B2 F23B1 F23B0 Unaffected = Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 F14B3 F14B2 F14B1 F14B0 F16B3 F16B2 F16B1 F16B0 F18B3 F18B2 F18B1 F18B0 F20B3 ...
Page 133
... Forty (40) bidirectional input-output (I/O) pins form six parallel ports. All I/O pins are programmable as inputs or outputs. Connect any unused I/O pins to an appropriate logic level, either Although the I/O ports do not require termination for proper operation, SS termination reduces excess current consumption and the possibility of electrostatic damage. Freescale Semiconductor NOTE MC68HC908LV8 Data Sheet, Rev 133 ...
Page 134
... DDRE7 DDRE6 DDRE5 DDRE4 PTE7 PTE6 PTE5 PPI1L R HDB5 Indeterminate = Unimplemented Figure 10-1. I/O Port Register Summary MC68HC908LV8 Data Sheet, Rev PTA4 PTA3 PTA2 PTA1 Unaffected by reset PTB4 PTB3 PTB2 PTB1 Unaffected by reset PTC4 PTC3 PTC2 PTC1 Unaffected by reset ...
Page 135
... T2SC0 ($0030) TIM2 T2SC1 ($0033) LCD LCDCR ($0051) CONFIG2 ($001D) LCD LCDCR ($0051) — — — — CONFIG2 ($001D) LCD LCDCR ($0051) MC68HC908LV8 Data Sheet, Rev. 2 Introduction Pin Control Bit KBIE0 PTA0/KBI0 KBIE1 PTA1/KBI1 KBIE2 PTA2/KBI2 KBIE3 PTA3/KBI3 PTA4/ADC0 PTA5/ADC1 ADCH[4:0] ...
Page 136
... CONFIG2 ($001D) LCD LCDCR ($0051 PTA6 PTA5 PTA4 Unaffected by Reset ADC2 ADC1 ADC0 Figure 10-2. Port A Data Register (PTA) Section 20. Keyboard Interrupt Module MC68HC908LV8 Data Sheet, Rev. 2 Pin Control Bit PTE0/FP3 PTE1/FP4 PTE2/FP5 PTE3/FP6 PEE LCDE PTE4/FP7 PTE5/FP8 PTE6/FP9 PTE7/FP10 ...
Page 137
... Table 10-2 summarizes the operation of the port A pins. Freescale Semiconductor NOTE DDRA6 DDRA5 DDRA4 DDRA3 NOTE DDRAx RESET PTAx Figure 10-4. Port A I/O Circuit MC68HC908LV8 Data Sheet, Rev Bit 0 DDRA2 DDRA1 DDRA0 Figure 10-4 shows the PTAx Port A 137 ...
Page 138
... DDRA[7:0] Input, Hi-Z Output DDRA[7: PTB6 PTB5 PTB4 Unaffected by reset FP1 T2CH1 T2CH0 High current sink Figure 10-5. Port B Data Register (PTB) NOTE MC68HC908LV8 Data Sheet, Rev. 2 Accesses to PTA Read Write (3) Pin PTA[7:0] PTA[7:0] PTA[7: Bit 0 PTB3 PTB2 PTB1 PTB0 T1CH1 ...
Page 139
... Chapter 6 Timer Interface Module Chapter 6 Timer Interface Module Chapter 9 Liquid Crystal Display (LCD DDRB6 DDRB5 DDRB4 DDRB3 NOTE MC68HC908LV8 Data Sheet, Rev. 2 (TIM). (TIM). 7.6.1 PPI Clock Source Select Driver Bit 0 DDRB2 DDRB1 DDRB0 Figure 10-7 shows the ...
Page 140
... Table 10-3. Port B Pin Functions Accesses to DDRB I/O Pin Mode Read/Write (2) DDRB[7:0] Input, Hi-Z Output DDRB[7: PPI1L HDB5 HDB4 HDB3 (PPI). (PPI). MC68HC908LV8 Data Sheet, Rev. 2 PTBX Accesses to PTB Read Write (3) Pin PTB[7:0] PTB[7:0] PTB[7: Bit 0 HDB2 PPI1CLKS1 PPI1CLKS0 Freescale Semiconductor ...
Page 141
... Unaffected by reset FP24 FP23 Figure 10-9. Port C Data Register (PTC) Chapter 9 Liquid Crystal Display (LCD DDRC6 DDRC5 DDRC4 DDRC3 NOTE MC68HC908LV8 Data Sheet, Rev Bit 0 PTC3 PTC2 PTC1 PTC0 FP22 FP21 FP20 FP19 Driver Bit 0 DDRC2 ...
Page 142
... Table 10-4. Port C Pin Functions Accesses to DDRC I/O Pin Mode Read/Write (2) DDRC[7:0] Input, Hi-Z Output DDRC[7: PTD6 PTD5 PTD4 PTD3 Unaffected by reset FP17 FP16 FP15 MC68HC908LV8 Data Sheet, Rev. 2 PTCx Accesses to PTC Read Write (3) Pin PTC[7:0] PTC[7:0] PTC[7: Bit 0 PTD2 PTD1 PTD0 FP14 FP13 FP12 ...
Page 143
... Freescale Semiconductor Driver DDRD6 DDRD5 DDRD4 DDRD3 NOTE DDRDx RESET PTDx Figure 10-14. Port D I/O Circuit MC68HC908LV8 Data Sheet, Rev. 2 Chapter 2 1 Bit 0 DDRD2 DDRD1 DDRD0 Figure 10-14 shows the PTDx Port D 143 ...
Page 144
... Accesses to DDRD I/O Pin Mode Read/Write (2) DDRD[7:0] Input, Hi-Z Output DDRD[7: PTE6 PTE5 PTE4 PTE3 Unaffected by reset FP9 FP8 FP7 Driver. MC68HC908LV8 Data Sheet, Rev. 2 Accesses to PTD Read Write (3) Pin PTD[7:0] PTD[7:0] PTD[7: Bit 0 PTE2 PTE1 PTE0 FP6 FP5 FP4 FP3 ...
Page 145
... NOTE DDREx RESET PTEx Figure 10-17. Port E I/O Circuit Table 10-6. Port E Pin Functions Accesses to DDRE I/O Pin Mode Read/Write (2) DDRE[7:0] Input, Hi-Z Output DDRE[7:0] MC68HC908LV8 Data Sheet, Rev Bit 0 DDRE2 DDRE1 DDRE0 Figure 10-14 shows the PTEx Accesses to PTE Read Write (3) Pin ...
Page 146
... Input/Output (I/O) Ports 146 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
Page 147
... When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: • Vector fetch or software clear • Return of the interrupt pin to logic one Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Figure 11-1 shows the 147 ...
Page 148
... V DD CLR IMASK MODE Figure 11-1. IRQ Module Block Diagram Bit Unimplemented Figure 11-2. IRQ I/O Register Summary MC68HC908LV8 Data Sheet, Rev. 2 4.5 Exception TO CPU FOR BIL/BIH INSTRUCTIONS IRQF IRQ SYNCHRONIZER INTERRUPT REQUEST HIGH TO MODE SELECT VOLTAGE DETECT LOGIC ...
Page 149
... ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch. Freescale Semiconductor NOTE NOTE is connected to the IRQ pin; this can be DD (SIM).) MC68HC908LV8 Data Sheet, Rev. 2 IRQ Module During Break Interrupts 149 ...
Page 150
... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only 150 IRQF Unimplemented MC68HC908LV8 Data Sheet, Rev Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...
Page 151
... Bit PPI1IE2 PPI1IE1 PPI1IE0 Unimplemented Figure 12-1. KBI I/O Register Summary Table 12-1. Pin Name Conventions Full MCU Pin Name PTA0/KBI0–PTA3/KBI3 MC68HC908LV8 Data Sheet, Rev KEYF 0 IMASKK ACKK KBIE3 KBIE2 KBIE1 ...
Page 152
... The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. 152 ACKK V DD RESET CLR KEYBOARD INTERRUPT FF MODEK MC68HC908LV8 Data Sheet, Rev. 2 INTERNAL BUS VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST IMASKK Freescale Semiconductor ...
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... Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 12.5 Keyboard Interrupt Registers Two registers control the operation of the keyboard interrupt module: • Keyboard status and control register • Keyboard interrupt enable register Freescale Semiconductor NOTE MC68HC908LV8 Data Sheet, Rev. 2 Keyboard Interrupt Registers 153 ...
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... Chapter 7 Programmable Periodic Interrupt 154 KEYF Unimplemented PPI1IE2 PPI1IE1 PPI1IE0 KBIE3 (PPI).) MC68HC908LV8 Data Sheet, Rev Bit 0 0 IMASKK MODEK ACKK Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...
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... To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Low-Power Modes 155 ...
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... Keyboard Interrupt Module (KBI) 156 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) Freescale Semiconductor SIM 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER Figure 13-1. COP Block Diagram MC68HC908LV8 Data Sheet, Rev. 2 SIM RESET CIRCUIT RESET STATUS REGISTER 157 ...
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... SIM counter. 13.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the CONFIG1 register. (See 3.3 Configuration Register 1 158 NOTE (RSR).). NOTE Figure 13-1. 13.4 COP Control (CONFIG1).) MC68HC908LV8 Data Sheet, Rev. 2 Register) clears the COP Freescale Semiconductor ...
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... The COP is disabled during a break interrupt when V Freescale Semiconductor (CONFIG1).) Low byte of reset vector Clear COP counter Unaffected by reset on the IRQ pin, the COP is disabled as long as V TST is present on the RST pin. TST MC68HC908LV8 Data Sheet, Rev. 2 COP Control Register 2 1 Bit 0 remains TST 159 ...
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... Computer Operating Properly (COP) 160 MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... TRIPR ≤ TRIPF FROM LVISR LVIIE EDGE DETECT LATCH CLR LVIOUT LVIIACK LVIIF TO LVISR FROM LVISR TO LVISR Figure 14-1. LVI Module Block Diagram MC68HC908LV8 Data Sheet, Rev. 2 pin DD . TRIPF LVISTOP FROM CONFIG1 LVI RESET LVI INTERRUPT REQUEST 161 ...
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... TRIPF falls below the V level. In the configuration register 1 DD TRIPF falls below the V level, an LVI reset will occur, and the LVIIE bit will TRIPF MC68HC908LV8 Data Sheet, Rev. 2 voltage. Clearing the LVI DD falls below a voltage configured for 5V TRIPF Specifications. goes above the rising 3V decreases to Section 5 ...
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... V DD Table 14-1. LVIOUT Bit Indication V LVIOUT DD > TRIPR < TRIPF < V < V Previous value TRIPF DD TRIPR MC68HC908LV8 Data Sheet, Rev. 2 LVI Status Register . V is greater than TRIPF TRIPR (CONFIG).) voltage was Bit trip voltage TRIPF ...
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... LVI module can generate a reset or an interrupt and bring the MCU out of stop mode. If enabled to generate both resets and interrupts, there will be no LVI interrupts, as resets have a higher priority. 164 NOTE MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 15.3 CPU Registers Figure 15-1 shows the five CPU registers. CPU registers are not part of the memory map. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 165 ...
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... HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 15-1. CPU Registers Unaffected by reset Figure 15-2. Accumulator ( Figure 15-3. Index Register (H:X) MC68HC908LV8 Data Sheet, Rev Bit 0 Bit Freescale Semiconductor ...
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... Figure 15-4. Stack Pointer (SP) NOTE Loaded with vector from $FFFE and $FFFF Figure 15-5. Program Counter (PC) MC68HC908LV8 Data Sheet, Rev. 2 CPU Registers Bit Bit 167 ...
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... The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result 168 NOTE MC68HC908LV8 Data Sheet, Rev Bit Freescale Semiconductor ...
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... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Arithmetic/Logic Unit (ALU) 169 ...
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... PC ← (PC rel ? ( ⊕ PC ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? ( ← (PC rel ? ( ← (PC rel ? ( MC68HC908LV8 Data Sheet, Rev. 2 Effect on CCR IMM A9 ii DIR ...
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... PC ← (PC rel ? (X) – (M) = $00 PC ← (PC rel ? (A) – (M) = $00 PC ← (PC rel ? (A) – (M) = $00 PC ← (PC rel ? (A) – (M) = $00 C ← ← 0 MC68HC908LV8 Data Sheet, Rev. 2 Instruction Set Summary Effect on CCR – – – – – – REL ...
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... M ← (M) – ← (H:A)/(X) H ← Remainder ⊕ A ← ← ( ← ( ← ( ← ( ← ( ← ( MC68HC908LV8 Data Sheet, Rev. 2 Effect on CCR DIR 3F dd INH 4F INH 5F 0 – – – INH ...
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... X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M) None A ← (A[3:0]:A[7:4]) A ← (A) | (M) Push (A); SP ← (SP) – 1 Push (H); SP ← (SP) – 1 Push (X); SP ← (SP) – 1 MC68HC908LV8 Data Sheet, Rev. 2 Instruction Set Summary Effect on CCR DIR BC dd EXT ...
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... A ← (A) – (M) – (C) C ← ← ← (A) (M ← (H:X) I ← 0; Stop Processing M ← (X) A ← (A) – (M) MC68HC908LV8 Data Sheet, Rev. 2 Effect on CCR – – – – – – INH 86 – – – – – – INH 8A – ...
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... Sign extend ← Loaded with ? If : Concatenated with Set or cleared — Not affected MC68HC908LV8 Data Sheet, Rev. 2 Opcode Map Effect on CCR – – 1 – – – INH 83 INH 84 – – – – – – INH 97 – – – – – – INH ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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... BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading the instruction register with the SWI instruction • Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode) Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 177 ...
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... The COP is disabled during a break interrupt when V 178 IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] CAUTION 4.7.3 SIM Break Flag Control Register is present on the RST pin. TST MC68HC908LV8 Data Sheet, Rev. 2 CONTROL BKPT (TO SIM) and the “Break Interrupts” Freescale Semiconductor ...
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... BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break routine. Reset clears the BRKA bit Break address match break address match Freescale Semiconductor BRKA Unimplemented MC68HC908LV8 Data Sheet, Rev. 2 Break Module (BRK Bit 179 ...
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... Writing a logic zero clears SBSW. MC68HC908LV8 Data Sheet, Rev Bit Bit Bit Bit Bit 0 SBSW R R (1) Note 0 Freescale Semiconductor ...
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... However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. Freescale Semiconductor MC68HC908LV8 Data Sheet, Rev. 2 Break Module (BRK Bit 181 ...
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... If $FFFE and $FFFF contain $FF (erased state security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. 182 ( reset vector is blank ($FFFE and $FFFF contain TST is applied to IRQ TST MC68HC908LV8 Data Sheet, Rev. 2 Figure 16-8 and Freescale Semiconductor ...
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... YES IS RESET POR? YES EXTENDED SECURITY = 00? INFINITE LOOP ENABLE FLASH MONITOR MODE ENTRY EXECUTE MONITOR CODE NO YES DOES RESET OCCUR? MC68HC908LV8 Data Sheet, Rev. 2 Monitor Module (MON) PTA0 = 1, NO PTA2 = 0? YES NORMAL INVALID USER MODE ARE ALL YES NO SECURITY BYTES CORRECT? NO ...
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... µ µ kΩ kΩ 74HC125 5 6 74HC125 MC68HC908LV8 Data Sheet, Rev. 2 MC68HC908LV8 V RST V DD OSC2 OSC1 10 kΩ PTA1 V TST IRQ 10 kΩ PTC3 10 kΩ PTA2 PTA0 V SS MC68HC908LV8 V RST ...
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... PTA1 OSC1 13 14 PTA2 PTC3 DD Table 16-1 by pulling RST low and then high. The MC68HC908LV8 Data Sheet, Rev. 2 Monitor Module (MON) Communication Speed COP External f op Clock 4.9152 2.4576 Disabled MHz MHz 9.8304 2.4576 Disabled MHz MHz 32.768 2 ...
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... RST after the initial reset to get into TST can be removed from the IRQ pin in the interest of freeing the IRQ TST to IRQ must be used to re-enter monitor mode after the next POR. TST, MC68HC908LV8 Data Sheet, Rev. 2 16.3.2 Security). After the is applied TST is maintained ...
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... Figure 16-10. Monitor Data Format MISSING STOP BIT APPROXIMATELY 2 BIT DELAY BEFORE ZERO ECHO Figure 16-11. Break Transaction Table 16-1. MC68HC908LV8 Data Sheet, Rev. 2 Monitor Module (MON) SWI SWI Vector High Vector Low $FFFC $FFFD $FEFC $FEFD NEXT START STOP BIT 7 ...
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... Figure 16-12. Read Transaction ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Figure 16-13. Write Transaction Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW MC68HC908LV8 Data Sheet, Rev. 2 DATA 2 3 RETURN DATA DATA Table 16-3 through Table 16-8. DATA RETURN Freescale Semiconductor ...
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... Freescale Semiconductor Command Sequence ADDRESS ADDRESS ADDRESS ADDRESS HIGH HIGH LOW LOW Command Sequence IREAD IREAD DATA Command Sequence FROM HOST DATA DATA IWRITE IWRITE ECHO MC68HC908LV8 Data Sheet, Rev. 2 Monitor Module (MON) DATA DATA DATA RETURN 189 ...
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... FROM HOST RUN RUN ECHO SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER MC68HC908LV8 Data Sheet, Rev LOW RETURN Freescale Semiconductor ...
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... RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank). Freescale Semiconductor NOTE Figure 16-15. 4096 + 32 CGMXCLK CYCLES FROM HOST FROM MCU NOTE MC68HC908LV8 Data Sheet, Rev. 2 Monitor Module (MON 191 ...
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... The Copy2RAM, rErase, and rProgram routines require certain registers and/or RAM locations to be initialized before calling the routines in the user software. and their locations. 192 NOTE ) is between 1.5 MHz and 8.0 MHz. op Table 16-9 MC68HC908LV8 Data Sheet, Rev between 1.5 MHz and 8.0 MHz. op shows variables used in the routines Freescale Semiconductor ...
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... DATA array size must match a programming or verifying range ) must be stored at CPUSPD, which is an address specified 2.1 MHz, the CPUSPD value is 8. Setting a op Table 16-10 provides necessary addresses used in the MC68HC908LV8 Data Sheet, Rev. 2 Routines Supported in ROM Description op (in MHz) × (in MHz) times 4. For example 193 ...
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... PTA0 = 0) placed with data read from FLASH I bit is preserved I bit is preserved Not Serviced Not Serviced N/A DATASIZE, ADDR (2 bytes), DATA array 6 bytes 11 bytes MC68HC908LV8 Data Sheet, Rev. 2 rErase rProgram $FF88 $FF8B Erase a PAGE or Program a FLASH entire array range 1.5 MHz to 1.5 MHz to 8.0 MHz 8.0 MHz ...
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... When the internal operating frequency is op (MON). Example 16-1. Receiving a Byte Serially ;GetByte jump address ;Configure port A bit input ;Call GetByte routine ;If C bit is clear, framing error occurred. ; Take a proper action NOTE MC68HC908LV8 Data Sheet, Rev. 2 Routines Supported in ROM Example 16-1 shows how to 195 ...
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... FLASH data in locations $FF00–$FF3F is copied to DATA array $0104–$0143. 196 Example 16-2. Sending a Byte Serially ;PutByte jump address ;Configure port A bit input ;Initialize data bit to zero PTA0=0 ;Load sent data $ ;Call PutByte routine MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...
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... FLASH NOTE ) and MASS erase time (t Erase (in MHz) times 4. For example 4.9152 MHz, the CPUSPD is 20 ($14). (in MHz) times 4. op MC68HC908LV8 Data Sheet, Rev. 2 Routines Supported in ROM applied on IRQ pin TST ) are set between 4 ms and MErase is 3.1 MHz, op 197 ...
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... RAM block start address $0120 ;CPUSPD location ;DATASIZE location ;ADDR location (2 bytes) ;DATA array start address ;fop = 4.9152MHz in this example ;Load any address within the page to ADDR ;Load RAM start address to H:X ;Call rErase routine MC68HC908LV8 Data Sheet, Rev TST Freescale Semiconductor ...
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... CPUSPD (Cycles) op prog CPUSPD ms). The Specifications. MC68HC908LV8 Data Sheet, Rev. 2 Routines Supported in ROM ) between 30 prog is 2.4576 MHz, the CPUSPD op t prog 35.1 µs < t ≤ 38.0 µs prog 33.0 µs ≤ t ≤ 39.4 µs prog µ s when programming a is defined as the cumulative high voltage µ ...
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... Fill DATA array, ;32 bytes data, values to program into FLASH ;(ie. 55, AA, 55, AA....) ;fop = 2.4576MHz in this example ;Load first address of the row to ADDR ;Load RAM block start address to H:X ;Call rProgram routine MC68HC908LV8 Data Sheet, Rev. 2 Freescale Semiconductor ...