mc68hc908lv8 Freescale Semiconductor, Inc, mc68hc908lv8 Datasheet - Page 162

• Manufacturer Part Number: mc68hc908lv8
• Description: M68hc08 Microcontrollers 8-bit Microcontroller With Integrated Lcd Driver
• Manufacturer: Freescale Semiconductor, Inc

Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V
reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V
V
The LVI trip point selection bits, LVISEL[1:0], select the trip point voltage, V
or 3V operation. The actual trip points are shown in
Setting LVI interrupt enable bit, LVIIE, enables LVI interrupts whenever the LVIOUT bit toggles (from logic
0 to logic 1, or from logic 1 to logic 0).
LVISTOP, LVIPWRD, LVIRSTD, and LVISEL[1:0] are in the configuration registers. See
Configuration Registers (CONFIG)
the MCU remains in reset until V
See
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR). The
LVIIE, LVIIF, and LVIIACK bits in the LVISR control LVI interrupt functions.
An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
14.3.1 Polled LVI Operation
In applications that can operate at V
the LVIOUT bit, or by setting the LVI interrupt enable bit, LVIIE, to enable interrupt requests. In the
configuration register 1 (CONFIG1), the LVIPWRD bit must be at logic 0 to enable the LVI module, and
the LVIRSTD bit must be at logic 1 to disable LVI resets.
The LVI interrupt flag, LVIIF, is set whenever the LVIOUT bit changes state (toggles). When LVIF is set,
a CPU interrupt request is generated if the LVIIE is also set. In the LVI interrupt service subroutine, LVIIF
bit can be cleared by writing a logic 1 to the LVI interrupt acknowledge bit, LVIIACK.
14.3.2 Forced Reset Operation
In applications that require V
module to reset the MCU when V
(CONFIG1), the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable
LVI resets.
If LVIIE is set to enable LVI interrupts when LVIRSTD is cleared, LVI reset has a higher priority over LVI
interrupt. In this case, when V
be cleared.
162
TRIPF
4.3.2.5 Low-Voltage Inhibit (LVI) Reset
. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
After a power-on reset (POR) the LVI’s default mode of operation is 3V.
If a 5V system is used, the user must modified the LVISEL[1:0] bits to raise
the trip point to 5V operation. Note that this must be done after every
power-on reset since the default will revert back to 3V mode after each
power-on reset. If the V
POR is released, the MCU will immediately go into reset. The LVI in this
case will hold the MCU in reset until either V
trip point, V
approximately 0V which will re-trigger the power-on reset.
TRIPR
DD
DD
, which will release reset or V
to remain above the V
DD
falls below the V
DD
for details of the LVI’s configuration bits. Once an LVI reset occurs,
DD
rises above a voltage, V
falls below the V
MC68HC908LV8 Data Sheet, Rev. 2
DD
levels below the V
supply is below the 3V mode trip voltage when
for details of the interaction between the SIM and the LVI.
TRIPF
NOTE
Chapter 17 Electrical
TRIPF
TRIPF
level, an LVI reset will occur, and the LVIIE bit will
TRIPF
level. In the configuration register 1
DD
level, enabling LVI resets allows the LVI
TRIPR
DD
level, software can monitor V
goes above the rising 3V
decreases to
, which causes the MCU to exit reset.
Specifications.
TRIPF
DD
voltage. Clearing the LVI
DD
, to be configured for 5V
falls below a voltage,
Freescale Semiconductor
Section 5.
DD
by polling