mc68hc908kx8 Freescale Semiconductor, Inc, mc68hc908kx8 Datasheet - Page 94

• Manufacturer Part Number: mc68hc908kx8
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

External Interrupt (IRQ)
The vector fetch or software clear and the return of the IRQ1 pin to logic 1 can occur in any order. The
interrupt request remains pending as long as the IRQ1 pin is at logic 0. A reset will clear the latch and the
MODE1 control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge sensitive only. With MODE1 clear, a vector fetch or
software clear immediately clears the IRQ1 latch.
The IRQF1 bit in the ISCR can be used to check for pending interrupts. The IRQF1 bit is not affected by
the IMASK1 bit, which makes it useful in applications where polling is preferred.
Use the branch if interrupt pin is high (BIH) or branch if interrupt pin is low (BIL) instruction to read the
logic level on the IRQ1 pin.
8.5 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR
has these functions:
IRQF1 — IRQ1 Flag Bit
ACK1 — IRQ1 Interrupt Request Acknowledge Bit
IMASK1 — IRQ1 Interrupt Mask Bit
MODE1 — IRQ1 Edge/Level Select Bit
94
•
•
•
•
This read-only status bit is high when the IRQ1 interrupt is pending.
Writing a 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as 0. Reset clears ACK1.
Writing a 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.
1 = IRQ1 interrupt pending
0 = IRQ1 interrupt not pending
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
1 = IRQ1 interrupt requests on falling edges and low levels
0 = IRQ1 interrupt requests on falling edges only
Shows the state of the IRQ1 interrupt flag
Clears the IRQ1 interrupt latch
Masks IRQ1 interrupt request
Controls triggering sensitivity of the IRQ1 interrupt pin
Address:
When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
Reset:
Read:
Write:
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 Data Sheet, Rev. 2.1
$001D
Bit 7
R
R
0
0
Figure 8-3. IRQ Status and Control Register (ISCR)
= Reserved
R
6
0
0
R
5
0
0
NOTE
R
U = Unaffected
4
0
0
IRQF1
R
U
3
ACK1
2
0
0
IMASK1
1
0
Freescale Semiconductor
MODE1
Bit 0
0