mc68hc05pv8a Freescale Semiconductor, Inc, mc68hc05pv8a Datasheet - Page 127

• Manufacturer Part Number: mc68hc05pv8a
• Description: Mc68hc05pv8a Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

9.3.2 Output Compare Registers
9.3.2.1 Output Compare Register 1
MC68HC(8)05PV8/A — Rev. 1.9
There are two output compare registers: Output compare register 1 and
output compare register 2. Output compare registers can be used for
several purposes such as controlling an output waveform or indicating
when a period of time has elapsed. All bits are readable and writeable
and are not altered by the timer hardware or reset. If the compare
function is not needed the two bytes of the output compare register can
be used as storage locations.
The 16-bit output compare register 1 is made up of two 8-bit registers at
locations $12 (MSB) and $13 (LSB). The output compare register
contents are compared with the contents of the free-running counter
once every four internal processor clock cycles. If a match is found, the
output compare flag OC1F (bit 5 of the timer status register ($1E)) is set
and the corresponding output level OLVL1 bit is clocked to TCMP1
output.
The output compare register values and the output level bit should be
changed after each successful comparison to establish a new elapsed
time-out. An interrupt can also accompany a successful output compare
provided the corresponding interrupt enable bit (OCI1E) is set.
After a processor write cycle to the output compare register 1 containing
the MSB ($12), the output compare function is inhibited until the LSB
($13) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($13) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register 1
without affecting the other byte. The output level (OLVL1) bit is clocked
to the output level register regardless of whether the output compare flag
(OC1F) is set or clear.
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16-Bit Programmable Timer
Technical Data
Registers