mc68hc05jp6pe Freescale Semiconductor, Inc, mc68hc05jp6pe Datasheet - Page 165

• Manufacturer Part Number: mc68hc05jp6pe
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

MC68HC05JJ6/MC68HC05JP6
Freescale Semiconductor
The planned action on the PB4/AN4/TCMP pin depends on the value
stored in the OLVL bit in the TCR, and it occurs when the value of the
16-bit free-running timer counter matches the value in the output
compare registers shown in
bits and are unaffected by reset.
Writing to the OCRH before writing to the OCRL inhibits timer compares
until the OCRL is written. Reading or writing to the OCRL after reading
the TCR will clear the output compare flag bit (OCF). The output
compare OLVL state will be clocked to its output latch regardless of the
state of the OCF.
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
Reset:
Reset:
$0016
$0017
Read:
Read:
Write:
Write:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This
5. Enable interrupts by clearing the I bit in the condition code
—
Figure 11-9. Output Compare Registers (OCRH and OCRL)
Rev. 3.2
written.
also clears the OCF flag bit in the TSR.
register.
Bit 15
Bit 7
Bit 7
Bit 7
Programmable Timer
14
6
6
6
13
5
5
5
Figure
Unaffected by Reset
Unaffected by Reset
12
4
4
4
11-9. These registers are read/write
11
3
3
3
General Release Specification
10
2
2
2
Programmable Timer
1
9
1
1
Bit 0
Bit 8
Bit 0
Bit 0
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