mc68hc05jp6pe Freescale Semiconductor, Inc, mc68hc05jp6pe Datasheet - Page 61

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mc68hc05jp6pe

Manufacturer Part Number
mc68hc05jp6pe
Description
M68hc05 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.3 Power-On Reset
5.4 External Reset
MC68HC05JJ6/MC68HC05JP6
Freescale Semiconductor
NOTE:
A positive transition on the V
power-on reset is strictly for conditions during powering up and cannot
be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t
becomes active allows the clock generator to stabilize. If the RESET pin
is at logic zero at the end of this multiple t
the reset condition until the signal on the RESET pin goes to a logic one.
A logic zero applied to the RESET pin for one and one half t
generates an external reset. This pin is connected to a Schmitt trigger
input gate to provide an upper and lower threshold voltage separated by
a minimum amount of hysteresis. The external reset occurs whenever
the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low
input will generate the internal RST signal that resets the CPU and
peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown
device that is activated by three internal reset sources. This RESET
pulldown device will be asserted only for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
Do not connect the RESET pin directly to V
some power supply designs if the internal pulldown on the RESET pin
should activate.
Rev. 3.2
Resets
DD
pin generates a power-on reset. The
CYC
CYC
DD
time, the MCU remains in
, as this may overload
General Release Specification
) after the oscillator
CYC
Resets
61

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