mpc8555e Freescale Semiconductor, Inc, mpc8555e Datasheet - Page 48

• Manufacturer Part Number: mpc8555e
• Description: Mpc8555e Powerquicc Iii Processor With Integrated Security
• Manufacturer: Freescale Semiconductor, Inc

CPM
Notes:
48
SDA/SCL fall time
Stop condition setup time
2. divider = f
1. F
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
In master mode: divider=BRGCLK/(f
In slave mode: divider=BRGCLK/(f
MAX
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
SDA
SCL
= BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
SCL
Characteristic
t
SCHDL
/prescaler.
t
SDHDL
t
SDLCL
t
SCLCH
SCL
Figure 31. CPM I2C Bus Timing Diagram
SCL
*prescaler)
*prescaler)=2*(I2BRG[DIV]+3)
Table 35. I2C Timing (continued)
Expression
t
t
SCHDH
t
SFALL
SCLDX
t
SRISE
t
SCHCL
2/(divider * f
t
SFALL
Min
-
SCL
All Frequencies
)
t
SDVCH
1/(33 * f
Max
t
Freescale Semiconductor
-
SCHDH
SCL
)
Unit
s
s