mpc8245ec Freescale Semiconductor, Inc, mpc8245ec Datasheet
mpc8245ec
Related parts for mpc8245ec
mpc8245ec Summary of contents
Page 1
... Overview The MPC8245 integrated processor is composed of a peripheral logic block and a 32-bit superscalar MPC603e core, as shown in Figure 1. © Freescale Semiconductor, Inc., 2001–2007. All rights reserved. MPC8245EC Rev. 10, 08/2007 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Electrical and Thermal Characteristics . . . . . . . . . . . . 5 5 ...
Page 2
Overview MPC8245 Processor Core Block Additional Features: • Prog I/O with Watchpoint • JTAG/COP Interface • Power Management Peripheral Logic Block Message Unit (with I DMA Controller Controller PIC 5 IRQs/ Interrupt 16 Serial ...
Page 3
The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and controller. The processor core is a full-featured, high-performance processor with floating-point support, memory ...
Page 4
Features – Write buffering for PCI and processor accesses – Normal parity, read-modify-write (RMW), or ECC – Data-path buffering between memory interface and processor – Low-voltage TTL logic (LVTTL) interfaces – 272 Mbytes of base and extended ROM/Flash/PortX space – ...
Page 5
Programmable interrupt controller (PIC) – Five hardware interrupts (IRQs serial interrupts – Four programmable timers with cascade — Two (dual) universal asynchronous receiver/transmitters (UARTs) — Integrated PCI bus and SDRAM clock generation — Programmable PCI bus and ...
Page 6
... PCI inputs with ± may be correspondingly stressed at voltages exceeding Note that this temperature range does not apply to the 400 MHz parts. For details, refer to the hardware specifications addendum MPC8245ECSO2AD. 4.1.2 Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8245. Some voltage values do not apply to the 400-MHz parts ...
Page 7
Table 2. Recommended Operating Conditions Characteristic PLL supply voltage—peripheral logic PCI reference Input voltage Die-junction temperature Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PCI pins are ...
Page 8
Electrical and Thermal Characteristics Figure 2 shows supply voltage sequencing and separation cautions 3 2 Power Supply Ramp Up Reset Configuration Pins HRST_CPU, HRST_CTRL Notes: 1. Numbers associated with waveform separations correspond to caution ...
Page 9
Figure 3 shows the undershoot and overshoot voltage of the memory interface GND – 0 GND – 1.0 V Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI ...
Page 10
Electrical and Thermal Characteristics Overvoltage Waveform Undervoltage Waveform Figure 5. Maximum AC Waveforms for 5-V Signaling 4.2 DC Electrical Characteristics Table 3 provides the DC electrical characteristics for the MPC8245 at recommended operating conditions. At recommended operating conditions (see Characteristic ...
Page 11
Table 3. DC Electrical Specifications (continued) At recommended operating conditions (see Characteristic Capacitance V Notes: 1. See Table 16 for pins with internal pull-up resistors. 2. See Table 4 for the typical drive capability of a specific signal pin based ...
Page 12
Electrical and Thermal Characteristics 4.3 Power Characteristics Table 5 provides power consumption data for the MPC8245. PCI Bus Clock/Memory Bus Clock/CPU Clock Frequency (MHz) Mode 66/66/266 66/133/266 Typical 1.7 2.0 (1.5) (1.8) Max—FP 2.2 2.4 (1.9) (2.1) Max—INT 1.8 2.1 ...
Page 13
Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC8245. For details, see “Thermal Management.” Characteristic Junction-to-ambient natural convection (Single-layer board—1s) Junction-to-ambient natural convection (Four-layer board—2s2p) Junction-to-ambient (@200 ft/min) (Single-layer board—1s) Junction-to-ambient (@200 ft/min) (Four layer board—2s2p) ...
Page 14
... Memory bus frequency PCI input frequency Notes: 1. For details, refer to the hardware specifications addendum MPC8245ECSO2AD. 2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating frequencies ...
Page 15
Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (see Num Characteristics and Conditions 16 DLL lock range for other modes 17 Frequency of operation (OSC_IN) 19 OSC_IN rise and fall times 20 OSC_IN duty cycle measured at ...
Page 16
Electrical and Thermal Characteristics Register settings that define each DLL mode are shown in DLL Mode Normal tap delay, No DLL extend Normal tap delay, DLL extend Max tap delay, No DLL extend Max tap delay, DLL extend The DLL_MAX_DELAY ...
Page 17
Figure 7. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0 MPC8245 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Propagation Delay Time ...
Page 18
Electrical and Thermal Characteristics 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 0 Figure 8. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1 MPC8245 Integrated Processor Hardware Specifications, Rev ...
Page 19
Figure 9. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0 MPC8245 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Propagation Delay Time ...
Page 20
Electrical and Thermal Characteristics 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 0 Figure 10. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1 4.5.2 Input AC Timing Specifications Table 10 provides the input AC timing ...
Page 21
Num 10a PCI input signals valid to PCI_SYNC_IN (input setup) 10b Memory input signals valid to sys_logic_clk (input setup) 10b0 Tap 0, register offset <0x77>, bits 5–4 = 0b00 10b1 Tap 1, register offset <0x77>, bits 5–4 = 0b01 10b2 ...
Page 22
Electrical and Thermal Characteristics Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and PCI_SYNC_IN, respectively. PCI_SYNC_IN sys_logic_clk T SDRAM_SYNC_IN (after DLL locks) Shown in 2:1 Mode 10b-d Memory Inputs/Outputs Input Timing Notes Midpoint ...
Page 23
Figure 13 shows the input timing diagram for mode select signals. HRST_CPU/HRST_CTRL Mode Pins Figure 13. Input Timing Diagram for Mode Select Signals 4.5.3 Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the MPC8245 ...
Page 24
Electrical and Thermal Characteristics Table 11. Output AC Timing Specifications (continued) Num 14b sys_logic_clk to output high impedance (for all others) Notes: 1. All PCI signals are measured from GV signal in question for 3.3 V PCI signaling levels. See ...
Page 25
Figure 15 provides the PCI_HOLD_DEL effect on output valid and hold times. PCI_SYNC_IN 12a2, 7.0 ns for 33 MHz PCI PCI_HOLD_DEL = 10 PCI Inputs/Outputs 33 MHz PCI 12a0, 6.0 ns for 66 MHz PCI PCI_HOLD_DEL = 00 PCI_HOLD_DEL = ...
Page 26
Electrical and Thermal Characteristics At recommended operating conditions with OV Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × OV and 0.9 × OV (max) DD ...
Page 27
Table 13. I All values refer to V (min) and V (max) levels (see IH IL Parameter Noise margin at the HIGH level for each connected device (including hysteresis) Note: 1. The symbols used for timing specifications follow the pattern ...
Page 28
Electrical and Thermal Characteristics Figure 17 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 4.7 PIC Serial Interrupt Mode AC Timing Specifications Table 14 provides the PIC serial interrupt mode AC ...
Page 29
VM sys_logic_clk 3 S_CLK VM S_FRAME S_RST Figure 18. PIC Serial Interrupt Mode Output Timing Diagram S_CLK S_INT Figure 19. PIC Serial Interrupt Mode Input Timing Diagram 4.8 IEEE 1149.1 (JTAG) AC Timing Specifications Table 15 provides the JTAG AC ...
Page 30
Electrical and Thermal Characteristics Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) (continued) Num Characteristic 11 TMS, TDI data hold time 12 TCK to TDO data valid 13 TCK to TDO high impedance Notes: 1. TRST is an asynchronous ...
Page 31
TCK TDI, TMS TDO TDO Figure 23. Test Access Port Timing Diagram 5 Package Description This section details package parameters, pin assignments, and dimensions. 5.1 Package Parameters The MPC8245 uses × 35 mm, cavity-up, 352-pin tape ball ...
Page 32
Package Description 5.2 Pin Assignments and Package Dimensions Figure 24 shows the top surface, side profile, and pinout of the MPC8245, 352 TBGA package. – F – CORNER ...
Page 33
Pinout Listings Table 16 provides the pinout listing for the MPC8245, 352 TBGA package. Name Pin Numbers C/BE[3:0] P25 K23 F23 A25 DEVSEL H26 FRAME J24 IRDY K25 LOCK J26 AD[31:0] V25 U25 U26 U24 U23 T25 T26 R25 ...
Page 34
Package Description Table 16. MPC8245 Pinout Listing (continued) Name Pin Numbers DQM[0:7] AB1 AB2 K3 K2 AC1 AC2 K1 J1 CS[0:7] Y4 AA3 AA4 AC4 FOE H1 RCS0 N4 RCS1 N2 RCS2/TRIG_IN AF20 RCS3/TRIG_OUT AC18 SDMA[1:0] ...
Page 35
Table 16. MPC8245 Pinout Listing (continued) Name Pin Numbers SOUT1/PCI_CLK0 AC25 SIN1/PCI_CLK1 AB25 SOUT2/RTS1/ AE26 PCI_CLK2 SIN2/CTS1/ AF25 PCI_CLK3 PCI_CLK0/SOUT1 AC25 PCI_CLK1/SIN1 AB25 PCI_CLK2/RTS1/ AE26 SOUT2 PCI_CLK3/CTS1/ AF25 SIN2 PCI_CLK4/DA3 AF26 PCI_SYNC_OUT AD25 PCI_SYNC_IN AB23 SDRAM_CLK [0: ...
Page 36
Package Description Table 16. MPC8245 Pinout Listing (continued) Name Pin Numbers QACK/DA0 F2 CHKSTOP_IN/ D14 SDMA14 TRIG_IN/RCS2 AF20 TRIG_OUT/RCS3 AC18 MAA[0:2] AF2 AF1 AE1 MIV A16 PMAA[0:1] AD18 AF18 PMAA[2] AE19 PLL_CFG[0:4]/ A22 B19 A21 B18 B17 DA[10:6] TEST0 AD22 ...
Page 37
Table 16. MPC8245 Pinout Listing (continued) Name Pin Numbers V AA24 AC16 AC19 AD12 AD6 AD9 DD C15 C18 C21 D11 D8 F3 H23 J3 L23 M3 R24 T4 V24 W4 No Connect D17 AV C17 AF24 ...
Page 38
Package Description Table 16. MPC8245 Pinout Listing (continued) Name Pin Numbers DA[14:15 Notes: 1. Place a pull-up resistor of 120 Ω or less on the TEST0 pin. 2. Treat these pins as no connects (NC) unless debug address ...
Page 39
PLL Configurations The internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and ...
Page 40
PLL Configurations Table 17. PLL Configurations (266- and 300-MHz Parts) (continued) 266-MHz Part PCI Clock PLL_CFG Input Ref. No. 10,13 [0:4] (PCI_ SYNC_IN) 1 Range (MHz 10011 10100 26 – 10101 12 ...
Page 41
Table 17. PLL Configurations (266- and 300-MHz Parts) (continued) 266-MHz Part PCI Clock PLL_CFG Input Ref. No. 10,13 [0:4] (PCI_ SYNC_IN) 1 Range (MHz 11111 Notes: 1. Limited by the maximum PCI input frequency (66 MHz). 2 Limited ...
Page 42
PLL Configurations Table 18. PLL Configurations (333- and 350-MHz Parts) (continued) PCI Clock Input PLL_ Ref 10,13 CFG[0:4] (PCI_ SYNC_IN) 1 Range (MHz 00010 50 –66 11, 00011 50 – ...
Page 43
Table 18. PLL Configurations (333- and 350-MHz Parts) (continued) PCI Clock Input PLL_ Ref 10,13 CFG[0:4] (PCI_ SYNC_IN) 1 Range (MHz 11110 Rev 11110 33 –47 Rev 11111 Notes: 1. Limited ...
Page 44
System Design 7 System Design This section provides electrical and thermal design recommendations for successful application of the MPC8245. 7.1 PLL Power Supply Filtering The AV and AV 2 power signals on the MPC8245 provide power to the peripheral logic/memory ...
Page 45
Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low inputs Connect unused active-high inputs tie to GND. All NC signals must remain unconnected. DD Power and ground connections ...
Page 46
System Design The following pins are reset configuration pins: GNT4/DA5, MDL[0], FOE, RCS0, CKE, AS, MCP, QACK/DA0, MAA[0:2], PMAA[0:2], SDMA[1:0], MDH[16:31], and PLL_CFG[0:4]/DA[10:15]. These pins are sampled during reset to configure the device. The PLL_CFG[0:4] signals are sampled a few ...
Page 47
SRESET, TRIG_IN, and TRIG_OUT. The default state (logic 1) of SDMA1 selects the MPC8240 backward-compatible mode functionality, while a logic 0 state on the SDMA1 signal selects extended ROM functionality. In extended ROM mode, the TBEN, CHKSTOP_IN, SRESET, TRIG_IN, and ...
Page 48
System Design reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 26 while ensuring that the target can ...
Page 49
From Target Board Sources (if any KEY 13 No pin 15 16 COP Connector Physical Pin Out Note: 1 QACK is an output and is not required at ...
Page 50
System Design 7.8 Thermal Management This section provides thermal management information for the tape ball grid array (TBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, heat sinks may be required to maintain junction temperature ...
Page 51
Figure 28. Die Junction-to-Ambient Resistance The board designer can choose between several types of heat sinks to place on the MPC8245. Several commercially-available heat sinks for the MPC8245 are ...
Page 52
System Design Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Selection of an appropriate heat sink depends on thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Other heat sinks offered by ...
Page 53
Adhesives and Thermal Interface Materials A thermal interface material placed between the top of the package and the bottom of the heat sink minimizes thermal contact resistance. For applications that attach the heat sink by a spring clip mechanism, ...
Page 54
System Design Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. Chanhassen, MN 55317 Internet: ...
Page 55
R is device-related and cannot be influenced by the user. The user controls the thermal environment to θJC change the case-to-ambient thermal resistance, R sink, the airflow around the device, the interface material, the mounting arrangement on the printed-circuit board, ...
Page 56
Document Revision History 8 Document Revision History Table 19 provides a revision history for this hardware specification. Revision Date 10 8/07 Section 3, Table to the chosen nominal does not exceed ± 100 mV. Completely replaced processor devices. 9 12/27/05 ...
Page 57
Table 19. Revision History Table (continued) Revision Date 5 — Section 4.1.2 — Added note 6 and related label for latching of the PLL_CFG signals. Section 4.1.3 — Updated specifications for the input high and input low voltages of PCI_SYNC_IN. ...
Page 58
Document Revision History Table 19. Revision History Table (continued) Revision Date 2 — Globally changed EPIC to PIC. Section 1.4.1.4—Note 5: Changed register reference from 0x72 to 0x73. Section 1.4.1.5—Table 5: Updated power dissipation numbers based on latest characterization data. ...
Page 59
Table 19. Revision History Table (continued) Revision Date 0.4 — Section 1.2—Changed Features list (format) to match with the features list of the MPC8245 Integrated Processor Reference Manual. Section 1.4.1.2—Updated Table 2 to include 1.8 ± 100mV numbers. Section 1.4.3—Changed ...
Page 60
Document Revision History Table 19. Revision History Table (continued) Revision Date 0.2 — Changed core supply voltage to 2.0 ± 100 mV in Section 1.3. (Supply voltage of 1.8 ± 100 longer recommended.) Changed rows 2, 5, ...
Page 61
Table 19. Revision History Table (continued) Revision Date 0.1 — Made V /AV DD Section 1.3, Table 2, Table 5, Table 9, Table 17, and Section 1.7.2. Pin D17, formerly LAV supplied internally. Eliminated all references to LAV Previous Note ...
Page 62
Ordering Information 9 Ordering Information Ordering information for the parts fully covered by this specification document is provided in “Part Numbers Fully Addressed by This Document.” Section 9.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers ...
Page 63
... Frequency ZU = TBGA 266 MHz, 300 MHz Lead-free 333 MHz, 350 MHz: TBGA 1 2.2 V for more information on available package types. Part Number Specification Markings (Document Order No. MPC8245ECS02AD Process 1 Package Descriptor ZU = TBGA V V= Lead-free TBGA for more information on available package types. ...
Page 64
Ordering Information 9.3 Part Marking Parts are marked as the example shown in MPC8245 Integrated Processor Hardware Specifications, Rev Figure 31. MPC8245LXXnnnx ATWLYYWW CCCCC MMMMM YWWLAZ Notes : MMMMM is the 5-digit mask number. ATWLYYWW is test traceability ...
Page 65
THIS PAGE INTENTIONALLY LEFT BLANK MPC8245 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Ordering Information 65 ...
Page 66
Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8245 Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...
Page 67
THIS PAGE INTENTIONALLY LEFT BLANK MPC8245 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Ordering Information 67 ...
Page 68
... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8245EC Rev. 10 08/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...