mpc8245ec Freescale Semiconductor, Inc, mpc8245ec Datasheet - Page 21

• Manufacturer Part Number: mpc8245ec
• Description: Mpc8245 Integrated Host Processor
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
Notes:
1. All PCI signals are measured from OV
2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in
3. Input timings are measured at the pin.
4. t
5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the
6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5–4
7. T
Num
10b0
10b1
10b2
10b3
11a0
11a1
11a2
11a3
10a
10b
10c
10d
10e
11a
11b
11c
11
3.3-V PCI signaling levels. See
question to the VM = 1.4 V of the rising edge of the memory bus clock, sys_logic_clk. sys_logic_clk is the same as
PCI_SYNC_IN in 1:1 mode but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every
rising and falling edge of PCI_SYNC_IN). See
VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See
of register offset <0x77> to select the desired input setup and hold times.
on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become
offset by the delay amount. To maintain phase-alignment of the memory clocks with respect to sys_logic_clk, the feedback
trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened to accommodate this range. The feedback
trace length is relative to the SDRAM clock output trace lengths. We recommend that the length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN be shortened by 0.7 ns because that is the midpoint of the range of T
range of T
For details on trace measurements and the problem of T
MPC8245/MPC8241 Memory Clock Design Guidelines.
CLK
os
represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present
is the time of one SDRAM_SYNC_IN clock cycle.
PCI input signals valid to PCI_SYNC_IN (input setup)
Memory input signals valid to sys_logic_clk (input setup)
Tap 0, register offset <0x77>, bits 5–4 = 0b00
Tap 1, register offset <0x77>, bits 5–4 = 0b01
Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)
Tap 3, register offset <0x77>, bits 5–4 = 0b11
PIC, misc. debug input signals valid to sys_logic_clk
(input setup)
I
Mode select inputs valid to HRST_CPU/HRST_CTRL (input setup)
T
sys_logic_clk to memory signal inputs invalid (input hold)
Tap 0, register offset <0x77>, bits 5–4 = 0b00
Tap 1, register offset <0x77>, bits 5–4 = 0b01
Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)
Tap 3, register offset <0x77>, bits 5–4 = 0b11
HRST_CPU/HRST_CTRL to mode select inputs invalid (input hold)
PCI_SYNC_IN to Inputs invalid (input hold)
2
os
C input signals valid to sys_logic_clk (input setup)
—SDRAM_SYNC_IN to sys_logic_clk offset time
os
to be reduced. Additional analyses of trace lengths and SDRAM loading must be performed to optimize timing.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
Figure
Characteristic
Table 10. Input AC Timing Specifications
DD
12.
/2 of the rising edge of PCI_SYNC_IN to 0.4 × OV
Figure
11.
os
, refer to the Freescale application note AN2164,
Figure
13.
9 × t
Min
3.0
2.6
1.9
1.2
0.5
3.0
3.0
0.4
0.7
1.4
2.1
1.0
0
0
CLK
Electrical and Thermal Characteristics
os
DD
and allows the impact from the
of the signal in question for
Max
1.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 3, 6
2, 3–5
2, 3, 6
2, 3, 5
1, 2, 3
1, 3
2, 3
2, 3
7
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