mpc8241tzq266c Freescale Semiconductor, Inc, mpc8241tzq266c Datasheet
mpc8241tzq266c
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mpc8241tzq266c Summary of contents
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... Overview The MPC8241 integrated processor is composed of a peripheral logic block and a 32-bit superscalar MPC603e core, as shown in Figure 1. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8241EC Rev. 10, 02/2009 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Electrical and Thermal Characteristics . . . . . . . . . . . . 6 5 ...
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Overview MPC8241 Processor Core Block Additional Features: • Prog I/O with Watchpoint • JTAG/COP Interface • Power Management Peripheral Logic Block Message Unit (with I 2 DMA Controller Controller PIC 5 IRQs/ Interrupt 16 ...
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The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART), memory controller, DMA controller, PIC interrupt controller, a message unit (and controller. The processor core is a full-featured, high-performance processor with floating-point support, memory ...
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Features – Write buffering for PCI and processor accesses – Normal parity, read-modify-write (RMW), or ECC – Data-path buffering between memory interface and processor – Low-voltage TTL logic (LVTTL) interfaces – 272 Mbytes of base and extended ROM/Flash/PortX space – ...
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I C controller with full master/slave support that accepts broadcast messages — Programmable interrupt controller (PIC) – Five hardware interrupts (IRQs serial interrupts – Four programmable timers with cascade — Two (dual) universal asynchronous receiver/transmitters (UARTs) ...
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Electrical and Thermal Characteristics 4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8241. 4.1 DC Electrical Characteristics This section covers ratings, conditions, and other characteristics. 4.1.1 Absolute Maximum Ratings ...
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Recommended Operating Conditions Table 2 provides the recommended operating conditions for the MPC8241. Table 2. Recommended Operating Conditions Characteristic Supply voltage I/O buffer supply for PCI and standard; supply voltages for memory bus drivers CPU PLL supply voltage PLL ...
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Electrical and Thermal Characteristics Figure 2 shows supply voltage sequencing and separation cautions 3 Power Supply Ramp Up Reset Configuration Pins HRST_CPU and HRST_CTRL Notes: 1. Numbers associated with waveform separations correspond to ...
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Figure 3 shows the undershoot and overshoot voltage of the memory interface. GV _OV GND/GNDRING GND/GNDRING – 0 GND/GNDRING – 1.0 V Figure 4 and Figure 5 show the undershoot and overshoot voltage ...
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Electrical and Thermal Characteristics Overvoltage Waveform Undervoltage Waveform Figure 5. Maximum AC Waveforms for 5-V Signaling 4.2 DC Electrical Characteristics Table 3 provides the DC electrical characteristics for the MPC8241 at recommended operating conditions. Characteristics Conditions Input high voltage PCI ...
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Table 3. DC Electrical Specifications (continued) Characteristics Conditions Capacitance MHz in Notes: 1. See Table 16 for pins with internal pull-up resistors. 2. All grounded pins are connected together. 3. Leakage current is ...
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Electrical and Thermal Characteristics 4.3 Power Characteristics Table 5 provides preliminary estimated power consumption data for the MPC8241. Mode 33/66/133 33/66/166 Typical 0.7 0.8 Max—CFP 0.8 1.0 Max—INT 0.8 0.9 Doze 0.5 0.6 Nap 0.2 0.2 Sleep 0.2 0.2 Mode ...
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Thermal Characteristics Table 6 provides the package thermal characteristics for the MPC8241. For details, see “Thermal Management.” Rating Junction-to-ambient natural Single-layer board (1s) convection Junction-to-ambient natural Four-layer board (2s2p) convection Junction-to-ambient (@200 ft/min) Single-layer board (1s) Junction-to-ambient (@200 ft/min) ...
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Electrical and Thermal Characteristics Table 7 provides the operating frequency information for the MPC8241 at recommended operating conditions (see Table 2) with LV Characteristic Processor frequency (CPU) Memory bus frequency PCI input frequency Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings ...
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Table 8. Clock AC Timing Specifications (continued) At recommended operating conditions (see Num Characteristics and Conditions 21 OSC_IN frequency stability Notes: 1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 through 2 Specification value ...
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Electrical and Thermal Characteristics Register settings that define each DLL mode are shown in DLL Mode Normal tap delay, No DLL extend Normal tap delay, DLL extend Max tap delay, No DLL extend Max tap delay, DLL extend The DLL_MAX_DELAY ...
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Figure 7. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=0 MPC8241 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Propagation Delay Time ...
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Electrical and Thermal Characteristics 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 0 Figure 8. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=1 MPC8241 Integrated Processor Hardware Specifications, Rev ...
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Figure 9. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=0 MPC8241 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor Propagation Delay Time ...
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Electrical and Thermal Characteristics 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 0 Figure 10. DLL Locking Range Loop Delay versus Frequency of Operation for DLL_Extend=1 4.5.2 Input AC Timing Specifications Table 10 provides the input AC timing ...
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Table 10. Input AC Timing Specifications (continued) Num 10b0 Tap 0, register offset <0x77>, bits 5:4 = 0b00 10b1 Tap 1, register offset <0x77>, bits 5:4 = 0b01 10b2 Tap 2, register offset <0x77>, bits 5:4 = 0b10 (default) 10b3 ...
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Electrical and Thermal Characteristics PCI_SYNC_IN sys_logic_clk T SDRAM_SYNC_IN (after DLL locks) Shown in 2:1 Mode 10b-d Memory Inputs/Outputs Input Timing Notes Midpoint voltage (1.4 V). 10b-d = Input signals valid timing. 11a = Input hold time of SDRAM_SYNC_IN ...
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Figure 13 shows the input timing diagram for mode select signals. HRST_CPU/HRST_CTRL Mode Pins Figure 13. Input Timing Diagram for Mode Select Signals 4.5.3 Output AC Timing Specification Table 11 provides the processor bus AC timing specifications for the MPC8241 ...
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Electrical and Thermal Characteristics Table 11. Output AC Timing Specifications (continued) Num 14b sys_logic_clk to output high impedance (for all others) Notes: 1. All PCI signals are measured from GV GV _OV of the signal in question for 3.3 V ...
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PCI_SYNC_IN 12a2, 7.0 ns for 33 MHz PCI PCI_HOLD_DEL = 10 PCI Inputs/Outputs 33 MHz PCI 12a0, 6.0 ns for 66 MHz PCI PCI_HOLD_DEL = 00 PCI_HOLD_DEL = 00 PCI Inputs/Outputs 66 MHz PCI PCI Inputs and Outputs Note: Diagram ...
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Electrical and Thermal Characteristics At recommended operating conditions with OV Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin (input voltage is between 0.1 × OV and 0.9 × OV (max) DD ...
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Table 13. I All values refer to V (min) and V (max) levels (see IH IL Parameter Noise margin at the HIGH level for each connected device (including hysteresis) Note: 1. The symbols used for timing specifications herein follow the ...
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Electrical and Thermal Characteristics Figure 17 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S 4.7 PIC Serial Interrupt Mode AC Timing Specifications Table 14 provides the PIC serial interrupt mode AC ...
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VM sys_logic_clk 3 S_CLK VM S_FRAME S_RST Figure 18. PIC Serial Interrupt Mode Output Timing Diagram S_CLK S_INT Figure 19. PIC Serial Interrupt Mode Input Timing Diagram 4.7.1 IEEE 1149.1 (JTAG) AC Timing Specifications Table 15 provides the JTAG AC ...
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Electrical and Thermal Characteristics Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) Num 11 TMS, TDI data hold time 12 TCK to TDO data valid 13 TCK to TDO high impedance Notes: 1. TRST is an asynchronous signal. The ...
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TCK TDI, TMS TDO TDO Figure 23. Test Access Port Timing Diagram 5 Package Description This section details package parameters, pin assignments, and dimensions. 5.1 Package Parameters for the MPC8241 The MPC8241 uses × 25 mm, cavity ...
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Package Description 5.2 Pin Assignments and Package Dimensions Figure 24 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZP package. Note that this is available for Rev. B parts only TOP VIEW ...
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Figure 25 shows the top surface, side profile, and pinout of the MPC8241, 357 PBGA ZQ and VR packages. Figure 25. MPC8241 Package Dimensions and Pinout Assignments (ZQ and VR Packages) MPC8241 Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor ...
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Package Description 5.3 Pinout Listings Table 16 provides the pinout listing for the MPC8241, 357 PBGA package. Signal Name Package Pin Number C/BE[3:0] V11 DEVSEL FRAME IRDY LOCK AD[31:0] U13 V13 U11 W14 V14 U12 W10 T10 ...
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Table 16. MPC8241 Pinout Listing (continued) Signal Name Package Pin Number RCS1 B9 RCS2/TRIG_IN P18 RCS3/TRIG_OUT N18 SDMA[1:0] A15 B15 SDMA[11:2] A11 B12 A12 C12 B13 C13 D12 A14 C14 B14 DRDY P1 SDMA12/SRESET L3 SDMA13/TBEN K3 SDMA14/CHKSTOP_IN K2 SDBA1 ...
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Package Description Table 16. MPC8241 Pinout Listing (continued) Signal Name Package Pin Number PCI_CLK1/SIN1 U16 PCI_CLK2/RTS1/SOUT2 W18 PCI_CLK3/CTS1/SIN2 V19 PCI_CLK4/DA3 V17 PCI_SYNC_OUT U17 PCI_SYNC_IN V18 SDRAM_CLK[0: SDRAM_SYNC_OUT B4 SDRAM_SYNC_IN A4 CKO/DA1 L1 OSC_IN R17 HRST_CTRL M2 ...
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Table 16. MPC8241 Pinout Listing (continued) Signal Name Package Pin Number TMS T18 TRST R16 GNDRING/GND F07 F08 F09 F10 F11 F12 F13 G07 G08 G09 G10 G11 G12 G13 H07 H08 H09 H10 H11 H12 H13 J07 J08 J09 ...
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Package Description Table 16. MPC8241 Pinout Listing (continued) Signal Name Package Pin Number DA[10:6 PLL_CFG[0:4] DA[11] T13 DA[12:13] M16 N16 DA[14:15 Notes: 1. Multi-pin signals such as AD[31:0] or MDL[0:31] physical package pin ...
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PLL Configuration The PLL_CFG[0:4] are configured by the internal PLLs. For a specific PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency of operation for the PCI-to-memory frequency multiplying and the ...
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PLL Configuration Table 17. PLL Configurations (166- and 200-MHz) (continued) 166 MHz-Part PCI Clock Peripheral PLL_CFG Input 2 Ref 1 [0:4] (PCI_ SYNC_IN) Bus Clock 3 Range (MHz 11110 Not usable 14 1F 11111 Not usable Notes: 1. ...
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Table 18. PLL Configurations (266-MHz Parts) (continued) PLL_ PCI Clock Input 2 Ref 10,11 CFG[0:4] (PCI_SYNC_IN 00110 12 7 (Rev. B) 00111 14 7 (Rev. D) 00111 8 01000 9 01001 A 01010 B 01011 C 01100 D ...
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System Design Information Table 18. PLL Configurations (266-MHz Parts) (continued) PLL_ PCI Clock Input 2 Ref 10,11 CFG[0:4] (PCI_SYNC_IN 11111 Notes: 1. Limited by maximum PCI input frequency (66 MHz). 2. Note the impact of the relevant revisions ...
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Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with minimal inductance of vias. ...
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System Design Information 7.4 Pull-Up/Pull-Down Resistor Requirements The data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. The data bus signals are: MDH[0:31], MDL[0:31], ...
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JTAG Configuration Signals Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While the TAP controller can ...
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System Design Information From Target Board Sources (if any Key KEY 13 No pin 15 16 COP Connector Physical Pin Out Notes: 1. QACK is an output ...
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Thermal Management This section provides thermal management information for the plastic ball grid array (PBGA) package for air-cooled applications. Depending on the application environment and the operating frequency, a heat sink may be required to maintain junction temperature within ...
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System Design Information 50.0 40.0 30.0 20.0 10.0 0.0 0 Figure 29. Die Junction-to-Ambient Resistance The board designer can choose among several types of heat sinks to place on the MPC8241. Several commercially available heat sinks for the MPC8241 are ...
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Internal Package Conduction Resistance For the PBGA, die-up, packaging technology, shown in resistance paths are as follows: • The die junction-to-case thermal resistance • The die junction-to-ball thermal resistance Figure 30 depicts the primary heat transfer path for a ...
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System Design Information 2 1 Figure 31. Thermal Performance of Select Thermal Interface Material The board designer can choose among several types of thermal interface. Heat sink adhesive materials are selected on the basis of ...
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Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 7.7.3 Heat Sink Usage An estimation of the chip junction temperature θJA ...
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Ordering Information where thermocouple temperature atop the package (°C) T ψ = thermal characterization parameter (°C/ power dissipation in package (W) D The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type ...
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Part Numbers Fully Addressed by This Document Table 19 provides the Freescale part numbering nomenclature for the MPC8241. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales ...
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Document Revision History Table 20. Part Numbers Addressed by MPC8241TXXPNS Series MPC nnnn T MPC 8241 T = Extended temperature spec. –40° to 105°C Notes: 1. See Section 5, “Package Description,” 2. Processor core frequencies supported by parts addressed by ...
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Table 21. Revision History Table (continued) Revision Date 8 12/19/2005 Document—Imported new template and made minor editoral corrections. Section 4.3.1—Before Figure 7, added paragraph for using DLL mode that provides lowest locked tap point read in 0xE3. Section 4.3.2—After Figure ...
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Document Revision History Table 21. Revision History Table (continued) Revision Date 4 — Section 1.4.1.2—Table 2: Changed note 1. Figure 2: Updated note 2 and removed ‘voltage regulator delay’ label since Section 1.7.2 is being deleted this revision. Also, updated ...
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Table 21. Revision History Table (continued) Revision Date 1 — Updated document template. Section 1.4.1.5—Updated driver type names in Table 4 so that they are consistent with the driver types referred to in the MPC8245 Integrated Processor Reference Manual. Added ...
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