mpc82x52at Megawin Technology, mpc82x52at Datasheet
mpc82x52at
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mpc82x52at Summary of contents
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... In-Application Program (IAP) ................................................................................63 Avoid Inadvertent Data Lost from IAP/ISP............................................................64 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2008 All rights reserved. MPC82x52A 8-bit micro-controller 2008/12 version A8 ...
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Instructions Set................................................................................................................65 Absolute Maximum Rating (MPC82E52A) ...................................................................68 DC Characteristics (MPC82E52A).................................................................................68 Absolute Maximum Rating (MPC82L52A) ...................................................................69 DC Characteristics (MPC82L52A).................................................................................69 Package Dimension.........................................................................................................70 Revision History .............................................................................................................72 2 MPC82x52A Data Sheet MEGAWIN ...
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Features Enhanced 80C51 Central Processing Unit 8 K bytes on-chip flash memory with ISP/IAP capability 256 bytes scratch-pad RAM Two-level code protection for flash memory access Two 16-bits timer/counter 7 sources, 4-level-priority interrupt capability One enhanced UART with automatic address ...
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... Package type: -PDIP-20: MPC82x52AE -SOP-20: MPC82E52AS -TSSOP-20: MPC82x52AT *: Tested by sampling 4 MPC82x52A Data Sheet MEGAWIN ...
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... The MPC82x52A is really the most efficient MCU adapted for simple control: electronic scales, remote controller, security encoder/decoder, and user interface controller. Order Information: Part Number Temperature Range MPC82x52AE Industrial MPC82x52AS Industrial MPC82x52AT Industrial MEGAWIN Package Packing PDIP-20 Tube SOP-20 Tube TSSOP-20 ...
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Pin Description Pin Definition Pin Name Pin Name RST 1 P3.0 (RXD) 2 P3.1 (TXD) 3 XTALO 4 XTALI 5 P3.2 (INT0) 6 P3.3 (INT1 TYPE DESCRIPTION ID RST high duty on this pin keeps for ...
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P3.4 (ECI/T0) 8 P3.5 (CEX1/T1) 9 VSS 10 P3.7 (CEX0) 11 P1.0 (AIN0) 12 P1.1 (AIN1) 13 MEGAWIN BU P3.4: = General purpose 4-state I/O port with internal pull-up mechanism; open-drain output. ECI: = External Clock Input to Programmable Counter ...
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P1.2 (AIN2) 14 P1.3 (AIN3) 15 P1.4 (SS/AIN4) 16 P1.5 17 (MOSI/AIN5) P1.6 18 (MISO/AIN6 P1.2: = General purpose 4-state I/O port with internal pull-up mechanism; open-drain output. AIN2: = Alternative ADC input BU P1.3: = General purpose ...
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P1.7 19 (SPICLK/AIN7) VCC 20 MEGAWIN BU P1.7: = General purpose 4-state I/O port with internal pull-up mechanism; can be configured as open-drain output. SPICLK: = Serial Clock for Serial Peripheral Interface (SPI) AIN7: = Alternative ADC input P Power ...
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Pin Configuration RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 ECI/T0/P3.4 CEX1/T1/P3.5 RXD/P3.0 TXD/P3.1 XTALO INT0/P3.2 INT1/P3.3 ECI/T0/P3.4 CEX1/T1/P3.5 10 RST XTALO 4 17 XTALI VSS 10 11 ...
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Block Diagram RAM ADDR Register B Register ACC BOD/BOR Control RESET Unit XTAL1 XTAL2 MEGAWIN RAM256 Stack Pointer TMP2 TMP1 ALU PSW WDT Port1 Latch Port3 Latch ADC Port1 Driver Port3 Driver 8 P1.0 ~ P1.7 P1.0 ~ P1.7 P3.0~P3.5,P3.7 ...
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Special Function Register Address Map PCAPWM0 ACC WDTCR D8 CCON CMOD D0 PSW SADEN B0 P3 P3M0 A8 IE SADDR A0 98 SCON SBUF 90 P1 P1M0 88 ...
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Bits Description SYMBOL DESCRIPTION SP Stack Pointer DPL Data Pointer Low DPH Data Pointer High SPISTAT SPI status register SPIF SPICTL SPI control register SSIG SPIDAT SPI data register PCON Power Control SMOD TCON Timer/Counter Control TMOD Timer/Counter Mode. GATE ...
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Byte IFADRL ISP Flash Address Low Byte IFMT ISP Mode Table SCMD ISP Serial Command ISPCR ISPEN ISP Control Register CL PCA Counter Low Byte CCAP0L Low byte of PCA module0 Compare/Capture register CCAP1L Low byte of PCA module1 Compare/Capture ...
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Memory Organization Address Space for MPC82x52A RAM AP Memory Address Space for MPC82x52A embedded Flash memory MEGAWIN 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, Access it via indirect addressing ...
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RAM There are 256 bytes RAM built in MPC82x52A. The user can visit the leading 128-byte RAM via direct addressing instructions, and we name those RAM as direct RAM that occupies address space 00h to 7Fh. Followed 128-byte RAM can ...
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ISPAS0}: = ISP-Address-Start {0,0}: = Set the ISP start address 1400 {0,1}: = Set the ISP start address 1800 {1,0}: = Set the ISP start address 1C00 {1,1}: = (default) Express no ISP code. HWBS: = HardWare-Boot-Selector 0: = ...
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The user must not clear the bi; otherwise, there could be inadvertent effect impacted on the device. OSCDN: = Used to adjust the behavior of crystal oscillator The current gain of crystal oscillator amplifier is reduced. It will ...
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The frequency of the clock source for the watch-dog-timer is divided by 64 {1,1,0}: = The frequency of the clock source for the watch-dog-timer is divided by 128 {1,1,1}: = The frequency of the clock source for the watch-dog-timer is ...
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Functional Description I/O Port Configuration All 15 port pins on MPC82x52A may be independently configured to one of four modes: quasi-bidirectional (standard 8051 port output), push-pull output, open-drain output or input-only. All port pins default to quasi-bidirectional after reset. Each ...
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Configuration of I/O port PxM0n PxM1n Quasi-bidirectional Mode Port pins in quasi-bidirectional output mode function similar ...
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Port latch data 22 VDD 2 clocks delay Strong Very weak Input data MPC82x52A Data Sheet VDD VDD Weak Port pin MEGAWIN ...
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Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains logic “0”. To use this configuration in application, a port pin must have an external ...
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Timer/Counter MPC82x52A has two 16-bit timers, and they are named T0 and T1. Each of them can also be used as a general event counter which counts the transition from Since the MPC82x52A is a RISC-like MCU ...
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SFR: TCON Bit-7 Bit-6 Bit-5 TF1 TR1 TF0 TF1: = Timer1 overflow flag. This bit is automatically set by hardware on T1 overflow, and will be automatically cleared by hardware when the processor vectors to the interrupt routine. TR1: = ...
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SFR: AUXR (Auxiliary Register) Bit-7 Bit-6 Bit-5 T0X12 T1X12 URM0X6 T0X12 clock source selector 0: = (default) Set the frequency of the clock source for T0 as the oscillator frequency divided-by-12. It will compatible to the traditional 80C51 ...
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Mode 0 The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TFx. The counted input is enabled to the timer when TRx = ...
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Mode 3 Timer1 in Mode3 simply holds its count, and the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such ...
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Interrupt There are seven interrupt sources available in MPC82x52A. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit (EA), which can ...
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The 33 interrupt is shared by the logical OR of PCA interrupt and LVD (Low-Voltage Detector) H interrupt. Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should poll them to ...
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ET0: =Interrupt controller of Timer-0 interrupt (default) Disable 1: = Enable EX0: =Interrupt controller of external interrupt- (default) Disable 1: = Enable SFR: IP(Interrupt Priority Low) Bit-7 Bit-6 Bit-5 - PPCA_LVD PSPI_ADC PPCA_LVD : = If ...
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IE0 /INT0 TF0 IE1 /INT1 TF1 RI TI SPI ESPI ADCI EADCI CF ECF CCF0 Individual Enable ECCF0 CCF1 ECCF1 LVF ENLVFI 32 IE Register IPH and IP Registers Global Enable Interrupt Control Block MPC82x52A Data Sheet Highest Priority Level ...
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Watch Dog Timer The watch dog timer in MPC82x52A consists of an 8-bit pre-scalar timer and a 15-bit timer. The timer is one-time enabled by setting ENW. Clearing ENW can not stop WDT counting. When the WDT is enabled, software ...
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WIDL: = Behavior controller of the WDT while the device is put under idle 0: = (default) Stop Watch Dog Timer counting 1: = Keep Watch Dog Timer counting (so further reset could happen) {PS2, PS1, PS0}: selector of the ...
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Universal Asynchronous Serial Port (UART) The serial port of MPC82x52A is duplex. It can transmit and receive simultaneously. The receiving and transmitting of the serial port share the same SFR SBUF, but actually there are two SBUF registers implemented in ...
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Mode3 Mode 3 is the same as mode 2 except the baud rate is variable. Baud Rate (for Mode 3) In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated ...
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SFR: SBUF (Serial Buffer) Bit-7 Bit-6 Bit-5 (data to be transmitted or received data) Frame Error Detection When used for frame error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE ...
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Programmable Counter Array (PCA) The Programmable Counter Array is a special 16-bit Timer that has two 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge ...
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CCF0 and CCF1 in SFR CCON. The CCF0 and CCF1 serve as flags for module-0 and module-1 respectively. They are set by hardware when either a match or a capture occurs. These flags also can only be cleared by ...
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CF:=PCA Counter overflow Flag This bit must be set by hardware itself. It can be cleared by software program. CR:=PCA Run control bit 0 := (default) Disable counting of the PCA counter 1 := Start counting of the PCA counter ...
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SFR: CL (PCA Counter Low Byte) Bit-7 Bit-6 Bit-5 SFR: CH (PCA Counter High Byte) Bit-7 Bit-6 Bit-5 SFR: CCAP0L (Low byte of PCA module-0 Compare/Capture register) Bit-7 Bit-6 Bit-5 Low Byte of the Compare/ Capture register in PCA Module ...
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ECOMn: = used to determine if Enable Comparator 0:= (default) Disable the comparator function 1:= Enable the comparator function CAPPn: = configure the module-n’s register to latch the PCA counter on Positive edge of EXIn or not 0:= (default) configure ...
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Configure PCA Module ECOMn CAPPn CAPNn MATn PCA Capture Mode To use ...
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High Speed Output Mode In this mode the CEXn output (port latch) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOGn, MATn, ...
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Write to CCAPnL Write to CCAPnH 0 1 Enable Write to CCAPnL Write to CCAPnH 0 1 Enable MEGAWIN CCAPnH CCAPnL 16-bit MATCH comparator ECOMn CAPPn CAPNn MATn TOGn 0 0 ...
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E n able C L overflow { [7:0]} < CnL , ...
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Serial Peripheral Interface (SPI) The device provides another high-speed serial communication interface, the SPI interface. The SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode 3Mbit/s can be supported in ...
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SPI-MODE-3. Many device declares that they meet SPI mechanism, but few of them are adaptive to all four modes. The MPC82x52A is flexible enough to be configured to communicate to another device with MODE-0, MODE-1, MODE-2 or MODE-3 SPI, and ...
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Set the clock rate of the SPI as the frequency of the clock source over 64. {1,1} := Set the clock rate of the SPI as the frequency of the clock source over 128. There are two extra SFRs make ...
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Typical Connection Master SPI single master single slave configurartion Master/Slave SPI dual device configuarion, where either can be a master or a slave Master SPI single master multiple slaves configurartion 50 MISO MISO MOSI MOSI SPICLK SPICLK Port Pin SS ...
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Communication In SPI, transfers are always initiated by the master. If the SPI is enabled(SPEN=1) and selected as master, any instruction that use SPI data register SPIDAT as the destination will starts the SPI clock generator and a data transfer. ...
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Typical Timing Diagram Clock Cycle SPICLK(CPOL=0) Driven from Master SPICLK(CPOL=1) Driven from Master MOSI (input) Driven from Master DORD=0 MISO (output) DORD=1 SS pin (if SSIG bit = 0 ) Driven from Master SPI slave transfer format with CPHA=0 Clock ...
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Clock Cycle SPICLK is strongly output-driving. SPICLK(CPOL=0) SPICLK(CPOL=1) SPEN=1 and MSTR=1, MOSI turns to output data MISO turns to input data DORD=0 MOSI (Output) DORD=1 MISO (Input) Driven from the target slave Target slave SS pin Control GPIO pin by ...
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Analog to Digital Converter P1.7(AIN7) P1.6(AIN6) P1.5(AIN5) P1.4(AIN4) P1.3(AIN3) P1.2(AIN2) P1.1(AIN1) P1.0(AIN0) 8-bit DAC The ADC on MPC82x52A is an 8-bit resolution, successive-approximation approach, and medium-speed A/D converter. V internal voltage-scaling DAC use, and the typical sink current on it ...
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SFR: ADCTL (ADC Control register) Bit-7 Bit-6 Bit-5 ADCON SPEED1 SPEED0 ADCON := When clear shut down the power of ADC block. When set turn on the power of ADC block. {SPEED1, SPEED0} := Conversion speed selector {0,0} := (default) ...
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Built-In Oscillator There is an oscillator built in the MPC82x52A which can be used as the oscillating source in replacing the external crystal oscillator in some specific applications. To enable the built-in oscillator, an user must configure the device by ...
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Power Management IDLE Mode An instruction setting PCON.0 causes the device go into the idle mode, and the internal clock is gated off to the CPU but not to the interrupt, timer, PCA, SPI, ADC, WDT and serial port functions. ...
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POWER-DOWN Mode An instruction setting PCON.1 causes the device go into the POWER-DOWN mode. In the POWER-DOWN mode, the on-chip oscillator is stopped. The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by either ...
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Reset and Boot Entrance There could be five conditions will cause the device to be reset. Power-Up RST pin press Watch Dog Timer overflows Power supply drops (option reset) Software invokes On the power-up moment, the device will load the ...
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In System Programming and In Application Programming In System Programming (ISP) To develop a good program for ISP function, the user has to understand the architecture of the embedded flash. The embedded flash consists of 16 pages. Each page contains ...
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Mode Selection 0 0 Standby 0 1 AP-memory read 1 0 AP-memory/Data-flash program AP-memory/Data-flash page erase 1 1 SFR: SCMD (ISP Sequential Command register to trigger ISP/IAP operation) Bit-7 Bit-6 Bit-5 SCMD is the command port for triggering ISP activity. ...
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Procedures demonstrating ISP function IFMT ← xxxxx011 B ISPCR ← 100xx010 IFADRH ← (page address high byte) IFADRL ← (page address low byte) SCMD ← 46h SCMD ← B9h (CPU progressing will be hold here ) (CPU ...
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Switching from ISP program to AP program The device permits the user normally start running his AP program as soon as the ISP program has finished updating the flash content. Just program an instruction at the tail of ISP program ...
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Avoid Inadvertent Data Lost from IAP/ISP If the user invoke ISP/IAP function in his application possible the MCU inadvertently jumps to those ISP/IAP statements while the power supply drops under specific level. The ISP/IAP statements could destroy the ...
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Instructions Set MNEMONIC MOV A, Rn Move register to Acc MOV A, direct Move direct byte o Acc MOV A, @Ri Move indirect RAM to Acc MOV A, #data Move immediate data to Acc MOV Rn, A Move Acc to ...
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MNEMONIC ANL A, Rn AND REGISTER TO ACC ANL A, direct AND DIRECT BYTE TO ACC ANL A, @Ri AND INDIRECT RAM TO ACC ANL A, #data AND IMMEDIATE DATA TO ACC ANL direct, A AND ACC TO DIRECT BYTE ...
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MNEMONIC ACALL addr11 ABSOLUTE SUBROUTINE CALL LCALL addr16 LONG SUBROUTINE CALL RET RETURN FROM SUBROUTINE RETI RETURN FROM INTERRUPT SUBROUTINE AJMP addr11 ABSOLUTE JUMP LJMP addr16 LONG JUMP SJMP rel SHORT JUMP JMP @A+DPTR JUMP INDIRECT RELATIVE TO DPTR JZ ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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Package Dimension 20-pin PDIP (MPC82x52AE) 20-pin SOP (MPC82x52AS) 70 MPC82x52A Data Sheet MEGAWIN ...
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... TSSOP-20(MPC82x52AT) MEGAWIN MPC82x52A Data Sheet 71 ...
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Revision History Version Date A1 2005/09 A2 2006/01 P6,7,38, A3 2006/08 P63 A4 2006/12 P52 2007/03 P63~P64 - Modify the storage temperature A5 A6 2007/11 P3~P4 A7 2007/ 2008/12 72 Page Description - Initial issue - Pin description ...