mpc82l54 Megawin Technology, mpc82l54 Datasheet
mpc82l54
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... In-Application Program (IAP) .......................................................................................63 Avoid Inadvertent Data Lost from IAP/ISP ...................................................................64 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2008 All rights reserved. MPC82x54A 8-bit micro-controller 2008/12 version A8 ...
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... Instructions Set................................................................................................................65 Absolute Maximum Rating (MPC82E54A) ...................................................................68 DC Characteristics (MPC82E54A).................................................................................68 Absolute Maximum Rating (MPC82L54A) ...................................................................69 DC Characteristics (MPC82L54A).................................................................................69 Package Dimension.........................................................................................................70 Revision History .............................................................................................................74 2 MPC82x54A Data Sheet MEGAWIN ...
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... The data endurance of the embedded flash gets over 20,000 times. - Greater than 100 years data rentention under room temperature Very low power consumption Operating Voltage: - 4.5V~5.5V for MPC82E54A - 2.4V~3.6V for MPC82L54A, minimum 2.7V requirement in flash write operation (ISP/ICP/…...) - Built-in Low-Voltage Detector and Reset circuit. Operating Temperature - Industrial (-40°C to +85°C)* ...
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More package type: PDIP-20/28:MPC82x54AE/AE2 PLCC-32: MPC82x54AP SOP-20/28:MPC82x54AS/AS2 SSOP-28: MPC82x54AS3 TSSOP-20/28:MPC82x54AT/AT2 *: Tested by sampling 4 MPC82x54A Data Sheet MEGAWIN ...
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General Description MPC82x54A is a single-chip 8-bit micro-controller with instruction sets fully compatible with industrial-standard 80C51 series microcontroller. There is an excellent MCU kernel built in this device compared to general 80C51 MCUs those take twelve oscillating cycles to finish ...
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Pin Description Pin Definition PIN NUMBER Pin Name PLCC-32 PDIP-28 PDIP- RST 3 3 P3.0 (RXD P3.1 (TXD P0.0 6 XTALO 7 6 XTALI 8 7 P3.2 (INT0 ...
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P0.1 10 P3.3 (INT1 P3.4 (ECI/T0 P3.5 (CEX1/T1 P2.4 (CEX3 P2 VSS MEGAWIN BU P0.1: = General purpose 4-state I/O port with internal pull-up mechanism; ...
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P2 P3.7 (CEX0 P1.0 (AIN0 P1.1 (AIN1 P1.2 (AIN2 P0.2 23 P1.3 (AIN3 P1.4 (SS/AIN4 P2.7: = General purpose 4-state I/O port with internal ...
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P0.3 26 P1.5 (MOSI/AIN5 P1.6 (MISO/AIN6 P1 (SPICLK/AIN7) P2.0 (CEX2 P2 VCC 32 28 MEGAWIN Alternative ADC input BU P0.3: = General purpose 4-state I/O port with internal pull-up mechanism; ...
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Pin Configuration 1 20 RST 2 19 RXD/P3 TXD/P3 XTAL2 5 XTAL1 16 6 INT0/P3 INT1/P3 ECI/T0/P3 CEX1/T1/P3 VSS SkinnyDIP-20/SOP-20/TSSOP-20 P3.1 P0.0 XTAL2 XTAL1 P3.2 P0.1 P3.3 ...
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Block Diagram AUX-RAM256 B Register ACC LVD/LVR Control RESET Unit XTAL1 XTAL2 MEGAWIN RAM ADDR RAM256 Register Stack Pointer TMP2 TMP1 ALU PSW WDT Port1 Latch ADC Port1 Driver 8 P1.0 ~ P1.7 P1.0 ~ P1.7 P3.0~P3.5,P3.7 MPC82x54 Block Diagram ...
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Special Function Register Address Map 0/8 1/9 0F8H CH 00000000 0F0H B 000000 0E8H CL 00000000 0E0H ACC WDTCR 00000000 0x000000 0D8H CCON CMOD 00xx0000 0xxxx000 0D0H PSW 00000000 0C8H 0C0H 0B8H IP SADEN x0000000 00000000 0B0H P3 P3M0 1x111111 ...
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Bits Description SYMBOL DESCRIPTION ADDR P0 Port 0 SP Stack Pointer DPL Data Pointer Low DPH Data Pointer High SPISTAT SPI Status register SPICTL SPI control register SPIDAT SPI data register PCON Power Control TCON Timer/Counter Control Register TMOD Timer/Counter ...
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PSW Program Status Word CCON PCA counter control register CMOD PCA counter mode register CCAPM0 PCA module0 mode register. CCAPM1 PCA module1 mode register. CCAP2M PCA module2 mode register CCAP3M PCA module3 mode register ACC Accumulator WDTCR WDT control register ...
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Memory Organization Address Space for MPC82x54A RAM AP Memory Address Space for MPC82x54A embedded Flash memory MEGAWIN 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, Access it via indirect addressing ...
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RAM There are 512 bytes RAM built in MPC82x54A. The user can visit the leading 128-byte RAM via direct addressing instructions, and we name those RAM as direct RAM that occupies address space 00h to 7Fh. Followed 128-byte RAM can ...
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ISPAS0}:= ISP-Address-Start {0,0}:= Set the ISP start address 3000 {0,1}:= Set the ISP start address 3400 {1,0}:= Set the ISP start address 3800 {1,1}:= (default) Express no ISP code. HWBS: = Hardware-Boot-Selector 0:= (default) Clearing the bit is to ...
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The user must not clear the bit; otherwise, there could be inadvertent effect impacted on the device. OSCDN: = Used to adjust the behavior of crystal oscillator. 0:= The current gain of crystal oscillator amplifier is reduced. It will bring ...
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The frequency of the clock source for the watch-dog-timer is divided by 8. {0,1,1}:= The frequency of the clock source for the watch-dog-timer is divided by 16 {1,0,0}:= The frequency of the clock source for the watch-dog-timer is divided ...
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Functional Description I/O Port Configuration All 27 port pins on MPC82x54A may be independently configured to one of four modes: quasi-bidirectional (standard 8051 port output), push-pull output, open-drain output or input-only. All port pins default to quasi-bidirectional after reset. Each ...
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SFR: P3M1 (P3 Configuration 1) Bit-7 Bit-6 Bit-5 P3M17 P3M16 P3M15 Configuration of I/O port PxM0n PxM1n ...
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Port latch data Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port register contains a logic “0”. To use this configuration in application, a port pin ...
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Push-pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port register contains a logic “1”. The push-pull mode may be used ...
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Timer/Counter MPC82x54A has two 16-bit timers, and they are named T0 and T1. Each of them can also be used as a general event counter, which counts the transition from Since the MPC82x54A is a RISC-like MCU ...
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SFR: TCON (Timer/Counter Control Register) Bit-7 Bit-6 Bit-5 TF1 TR1 TF0 TF1: = Timer1 overflow flag. This bit is automatically set by hardware on T1 overflow, and will be automatically cleared by hardware when the processor vectors to the interrupt ...
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SFR: AUXR (Auxiliary Register) Bit-7 Bit-6 Bit-5 T0X12 T1X12 URM0X6 T0X12 clock source selector 0:= (default) Set the frequency of the clock source for T0 as the oscillator frequency divided-by-12. It will compatible to the traditional 80C51 MCU. ...
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Mode 0 The timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TFx. The counted input is enabled to the timer when TRx = ...
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Mode 3 Timer1 in Mode3 simply holds its count, and the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 as two separate 8-bit counters. TL0 uses the Timer0 control bits such ...
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Interrupt There are seven interrupt sources available in MPC82x54A. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit (EA), which can ...
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Neither of these flags is cleared by hardware when the service routine is vectored to. The service routine should poll them to determine which one to request service and it will be cleared by software. All of the bits ...
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ET0:=Interrupt controller of Timer-0 interrupt. 0:=(default) Disable 1:= Enable EX0:=Interrupt controller of external interrupt-0. 0:=(default) Disable 1:= Enable SFR: IP (Interrupt Priority Low) Bit-7 Bit-6 Bit-5 - PPCA_LVD PSPI_ADC PPCA_LVD := If set, Set priority for PCA /LVF interrupt higher ...
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IE0 /IN T0 TF0 IE1 /IN T1 TF1 RI TI SPI ESPI A UXR.3 ADCI EADCI A UXR.4 Individual Enable CCF0 ECCF0 CCF1 ECCF1 CCF2 ECCF2 CCF3 ECCF3 CF ECF LVF ENLVFI 32 IE Register IPH and IP Registers Global ...
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Watch Dog Timer The watch dog timer in MPC82x54A consists of an 8-bit pre-scalar timer and a 15-bit timer. The timer is one-time enabled by setting ENW. Clearing ENW can not stop WDT counting. When the WDT is enabled, software ...
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WIDL: = Behavior controller of the WDT while the device is put under idle 0:= (default) Stop Watch Dog Timer counting 1:= Keep Watch Dog Timer counting (so further reset could happen) {PS2, PS1, PS0 }: selector of the WDT ...
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Universal Asynchronous Serial Port (UART) The serial port of MPC82x54A is duplex. It can transmit and receive simultaneously. The receiving and transmitting of the serial port share the same SFR SBUF, but actually there are two SBUF registers implemented in ...
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Mode3 Mode 3 is the same as mode 2 except the baud rate is variable. Baud Rate (for Mode 3) In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated ...
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SFR: SBUF (Serial Buffer) Bit-7 Bit-6 Bit-5 (data to be transmitted or received data) Frame Error Detection When used for frame error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE ...
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Programmable Counter Array (PCA) The Programmable Counter Array is a special 16-bit Timer that has four 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge ...
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CF bit (CCON.7) will be set when the PCA timer overflows, and an interrupt will be generated if the ECF (CMOD.0) is set. The CF bit can only be cleared by software. There are four bits named CCF0, CCF1, CCF2 ...
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CF := PCA Counter overflow Flag This bit must be set by hardware itself. It can be cleared by software program PCA Run control bit 0:= (default) Disable counting of the PCA counter 1:= Start counting of the ...
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If both bits are set, both edges will be enabled, and a capture will occur for either transition. The bit ECOMn when set enables the comparator function. SFR: CL (PCA Counter Low Byte) Bit-7 Bit-6 Bit-5 SFR: CH (PCA ...
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ECOM1 CAPP1 SFR: CCAPM2 (PCA Module-2 Mode Register) Bit-7 Bit-6 Bit-5 - ECOM2 CAPP2 SFR: CCAPM3 (PCA Module-3 Mode Register) Bit-7 Bit-6 Bit-5 - ECOM3 CAPP3 ECOMn := used to determine if Enable Comparator 0:= (default) Disable the comparator ...
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Configure PCA Module ECOMn CAPPn CAPNn MATn PCA Capture Mode To use ...
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High Speed Output Mode In this mode, the CEXn output (port latch) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOGn, MATn, ...
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Write to CCAPnL Write to CCAPnH 0 1 Enable Write to CCAPnL Write to CCAPnH 0 1 Enable MEGAWIN CCF3 CCF2 CCAPnH CCAPnL 16-bit MATCH comparator ECOMn CAPPn CAPNn MATn TOGn 0 0 ...
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E n able C L overflow { [7:0]} < CnL , ...
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Serial Peripheral Interface (SPI) The device provides another high-speed serial communication interface, the SPI interface. The SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode 3Mbit/s can be supported in ...
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SPI-MODE-0, SPI-MODE-1, SPI-MODE-2, and SPI-MODE-3. Many device declares that they meet SPI mechanism, but few of them are adaptive to all four modes. The MPC82x54A is flexible enough to be configured to communicate ...
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Set the clock rate of the SPI as the frequency of the clock source over 64. {1,1}: = Set the clock rate of the SPI as the frequency of the clock source over 128. There are two extra ...
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Typical Connection Master SPI single master single slave configurartion Master/Slave SPI dual device configuarion, where either can be a master or a slave Master SPI single master multiple slaves configurartion 50 MISO MISO MOSI MOSI SPICLK SPICLK Port Pin SS ...
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Communication In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN=1) and selected as master, any instruction that use SPI data register SPIDAT as the destination will starts the SPI clock generator and a data ...
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Typical Timing Diagram Clock Cycle SPICLK(CPOL=0) Driven from Master SPICLK(CPOL=1) Driven from Master MOSI (input) Driven from Master DORD=0 MISO (output) DORD=1 SS pin (if SSIG bit = 0 ) Driven from Master SPI slave transfer format with CPHA=0 Clock ...
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Clock Cycle SPICLK is strongly output-driving. SPICLK(CPOL=0) SPICLK(CPOL=1) SPEN=1 and MSTR=1, MOSI turns to output data MISO turns to input data DORD=0 MOSI (Output) DORD=1 MISO (Input) Driven from the target slave Target slave SS pin Control GPIO pin by ...
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Analog to Digital Converter P1.7(AIN7) P1.6(AIN6) P1.5(AIN5) P1.4(AIN4) P1.3(AIN3) P1.2(AIN2) P1.1(AIN1) P1.0(AIN0) 10-bit DAC The ADC on MPC82x54A is an 10-bit resolution, successive-approximation approach, and medium-speed A/D converter. V internal voltage-scaling DAC use, and the typical sink current on it ...
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SFR: ADCTL (ADC Control register) Bit-7 Bit-6 Bit-5 ADCON SPEED1 SPEED0 ADCON := When clear shut down the power of ADC block. When set turn on the power of ADC block. {SPEED1, SPEED0}:= Conversion speed selector {0,0}:= (default) A conversion ...
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... The threshold voltage depends on temperature change. Lower the temperature goes, higher the threshold voltage rises. During temperature scope (-40℃, 85℃), the threshold voltage falls between scope (2.7V, 1.8V) for MPC82L54, and (4.2V, 3.2V) for MPC82E54. To control the low-voltage detection and reset, also the use must read another document “ ...
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Power Management IDLE Mode An instruction setting PCON.0 causes the device go into the idle mode, the internal clock is gated off to the CPU but not to the interrupt, timer, PCA, SPI, ADC, WDT and serial port functions. There ...
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POWER-DOWN Mode An instruction setting PCON.1 causes the device go into the POWER-DOWN mode. In the POWER-DOWN mode, the on-chip oscillator is stopped. The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by either ...
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Reset and Boot Entrance There could be five conditions will cause the device to be reset. Power-Up RST pin press Watch Dog Timer overflows Reset from Low-Voltage-Detector Software invokes The following procedure describes how does this device select the boot ...
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In System Programming and In Application Programming In System Programming (ISP) To develop a good program for ISP function, the user has to understand the architecture of the embedded flash. The embedded flash consists of 31 pages. Each page contains ...
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Mode Selection SFR: SCMD (ISP Sequential Command register to trigger ISP/IAP operation) Bit-7 Bit-6 Bit-5 SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46 ISPCR.7 ...
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Procedures demonstrating ISP function IFMT ← xxxxx011 B ISPCR ← 100xx010 IFADRH ← (page address high byte) IFADRL ← (page address low byte) SCMD ← 46h SCMD ← B9h (CPU progressing will be hold here ) (CPU continues) IFMT ← ...
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Switching from ISP program to AP program The device permits the user normally start running own AP program as soon as the ISP program has finished updating the flash content. Just program an instruction at the tail of ISP program ...
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Avoid Inadvertent Data Lost from IAP/ISP If the user invoke ISP/IAP function in own application possible the MCU inadvertently jumps to those ISP/IAP statements while the power supply drops under specific level. The ISP/IAP statements could destroy the ...
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Instructions Set MNEMONIC MOV A, Rn Move register to Acc MOV A, direct Move direct byte o Acc MOV A, @Ri Move indirect RAM to Acc MOV A, #data Move immediate data to Acc MOV Rn, A Move Acc to ...
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MNEMONIC ANL A, Rn AND REGISTER TO ACC ANL A, direct AND DIRECT BYTE TO ACC ANL A, @Ri AND INDIRECT RAM TO ACC ANL A, #data AND IMMEDIATE DATA TO ACC ANL direct, A AND ACC TO DIRECT BYTE ...
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MNEMONIC ACALL addr11 ABSOLUTE SUBROUTINE CALL LCALL addr16 LONG SUBROUTINE CALL RET RETURN FROM SUBROUTINE RETI RETURN FROM INTERRUPT SUBROUTINE AJMP addr11 ABSOLUTE JUMP LJMP addr16 LONG JUMP SJMP rel SHORT JUMP JMP @A+DPTR JUMP INDIRECT RELATIVE TO DPTR JZ ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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... IL2 I Input Leakage current(Open-Drain output Logic transition current(P1,3) H2L I Operating current OP I Idle mode current IDLE I Power down current PD R Internal reset pull-down resistance RST MEGAWIN (MPC82L54A) -55 ~ +125 - 150 -0.3 ~ VCC + 0.3 -0.3 ~ +4.2 Test Condition Vcc=3.3V Vcc=3.3V Vcc=3.3V V =0.45V PIN V =2.4V PIN V =2.4V PIN V =0 ...
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Package Dimension 20-pin PDIP (MPC82X54AE) 28-pin PDIP (MPC82X54AE2) 70 MPC82x54A Data Sheet MEGAWIN ...
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SOP (MPC82X54AS) 28-pin SOP (MPC82X54AS2) MEGAWIN MPC82x54A Data Sheet 71 ...
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TSSOP (MPC82X54AT) 28-pin TSSOP (MPC82X54AT2) 72 MPC82x54A Data Sheet MEGAWIN ...
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PLCC (MPC82X54AP) 28-pin SSOP (MPC82X54AS3) MEGAWIN MPC82x54A Data Sheet 73 ...
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Revision History Version Date A1 2006/01 A2 2006/01 A3 2006/08 A4 2006/12 P55 A5 2007/03 P67 2007/ 2007/ 2008/12 74 Page Description - Initial issue. - Increase available package SSOP-28. - Revises the possible ...