mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet
mpc8313e
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mpc8313e Summary of contents
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... The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an enhanced local bus controller, a 32-bit PCI controller, a dedicated security This document contains information on a new product ...
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... GPIO I/O Sequencer (IOS) DMA PCI The MPC8313E’s security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. 1.1 MPC8313E Features The following features are supported in the MPC8313E. ...
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... Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and HMAC with any algorithm • One crypto-channel supporting multi-command descriptor chains 1.4 DDR Memory Controller The MPC8313E DDR1/DDR2 memory controller includes the following features: • Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM • Support for up to 333-MHz • ...
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... Overview 1.6 USB Dual-Role Controller The MPC8313E USB controller includes the following features: • Supports USB on-the-go mode, which includes both device and host functionality, when using an external ULPI (UTMI + low-pin interface) PHY • Complies with USB Specification, Rev. 2.0 • Supports operation as a stand-alone USB device — ...
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... The PIC programming model supports 5 external and 34 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. 1.9 Power Management Controller (PMC) The MPC8313E power management controller includes the following features: • Provides power management when the device is used in both host and agent modes • ...
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... FIFOs are supported for both the transmitter and the receiver. The MPC8313E local bus controller (LBC) port allows connections with a wide variety of external DSPs and ASICs. Three separate state machines share the same external pins and can be programmed separately to access different types of devices ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8313E. The MPC8313E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation shown in Figure 3. 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8313E. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic ...
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... Supply for eLBCIOs Analog and Digital Ground Notes: 1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction–either in the positive or negative direction. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8313E. G/L/NV + 20% DD G/L/ ...
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... Power Sequencing The MPC8313E does not require the core supply voltage and IO supply voltages to be applied in any particular order. Note that during the power ramp-up, before the power supplies are stable, there might be a period when IO pins are actively driven. After the power is stable, as long as PORESET is asserted, most IO pins are tri-stated ...
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... IO voltage and assert PORESET before the power supplies fully ramp up. 3 Power Characteristics The estimated typical power dissipation for this family of MPC8313E devices is shown in Table 5 shows the estimated typical I/O power dissipation. . Core Frequency (MHz) 267 333 Note: 1 ...
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... Power Characteristics Table 5. MPC8313E Typical I/O Power Dissipation (continued) TSEC I/O load = 20pF MII, 25MHz RGMII, 125MHz USBDR controller 60 MHz load = 20pF Other I/O MPC8313E PowerQUICC 12 0.008 0.015 ™ II Pro Processor Hardware Specifications, Rev Multiple by number of 0.044 W interface used 0.078 W W Freescale Semiconductor ...
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... V ≤ V PCI_SYNC_IN Input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E. Table 7. SYS_CLK_IN AC Timing Specifications Parameter/Condition ...
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... RESET Initialization 5 RESET Initialization This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8313E. 5.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage ...
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... SYS_CLK_IN only valid when the device is in PCI host mode. SYS_CLK_IN 3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV. Table 10 provides the PLL lock times. Parameter/Condition PLL lock times MPC8313E PowerQUICC Freescale Semiconductor — 1 Table 10. PLL Lock Times Min Max — ...
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... Output leakage is measured with all outputs disabled Table 12 provides the DDR2 capacitance when Table 12. DDR2 SDRAM Capacitance for GV Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled MPC8313E PowerQUICC 16 Symbol Min GV 1.7 DD 0.49 × REF ...
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... Note: 1. This parameter is sampled (peak-to-peak) = 0.2 V. OUT Table 15 provides the current draw characteristics for MV Table 15. Current Draw Characteristics for MV Parameter / Condition Current draw for MV 1. The voltage regulator for MV MPC8313E PowerQUICC Freescale Semiconductor Symbol Min GV 2.3 DD 0.49 × REF V MV – ...
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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t can be determined by the following equation: t and abs the absolute value of t CISKEW MPC8313E PowerQUICC 18 of 1.8 ±5% DD Symbol Min V — ...
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... ADDR/CMD output hold with respect to MCK MCS[n] output setup with respect to MCK MCS[n] output hold with respect to MCK MCK to MDQS Skew MDQ//MDM output setup with respect to MDQS MDQ//MDM output hold with respect to MDQS MPC8313E PowerQUICC Freescale Semiconductor 1 Symbol Min t ...
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... DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8313E PowerQUICC II Pro Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...
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... DUART DC Electrical Characteristics Table 20 provides the DC electrical characteristics for the DUART interface. Table 20. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage NVDD High-level output voltage, = –100 μ MPC8313E PowerQUICC Freescale Semiconductor t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX ...
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... Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8 th values are sampled each 16 MPC8313E PowerQUICC 22 V — — IN Table 21. DUART AC Timing Specifications ...
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... V IL Input high current I IH Input low current I IL Note: 1. The symbol this case, represents the LV IN MPC8313E PowerQUICC Freescale Semiconductor Characteristics.” 23. The potential applied to the input of a MII, RGMII, SGMII, or RTBI Conditions — –4 DDA DDB ...
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... MII transmit AC timing specifications. Table 24. MII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay MPC8313E PowerQUICC 24 Conditions /LV — DDB I = –1 ...
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... Table 25. MII Receive AC Timing Specifications At recommended operating conditions with LV Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK MPC8313E PowerQUICC Freescale Semiconductor / LV /NV of 3.3 V ± 10%. DDA DDB ...
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... R (rise (fall). Figure 8 provides the AC test load for TSEC. Output Figure 9 shows the MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications MPC8313E PowerQUICC /NV of 3.3 V ± 10%. DDA DDB DD 1 Symbol ...
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... RMII receive AC timing specifications. Table 27. RMII Receive AC Timing Specifications At recommended operating conditions with NV Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK MPC8313E PowerQUICC Freescale Semiconductor of 3.3 V ± 10 Symbol t RMX ...
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... RGMII and RTBI AC Timing Table 28 presents the RGMII and RTBI AC timing specifications. Table 28. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 3 Clock cycle duration MPC8313E PowerQUICC 28 of 3.3 V ± 10 Symbol t RMXR (min) t ...
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... RGMII and RTBI AC timing and multiplexing diagrams. GTX_CLK (At Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 13. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8313E PowerQUICC Freescale Semiconductor /LV of 2.5 V ± 5%. DDA DDB t /t RGTH RGT RGTH ...
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... Input high voltage V IH Input low voltage V IL Input high current I IH Input low current I IL Note: 1. Note that the symbol this case, represents the LV IN MPC8313E PowerQUICC 30 Section 8.1, “Enhanced Three-Speed Ethernet Table 29 and Conditions — –1 Min OH DDA DDB ...
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... MDC latter convention is used with the appropriate letter: R (rise (fall). Figure 14 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 14. MII Management Interface Timing Diagram MPC8313E PowerQUICC Freescale Semiconductor /LV is 3.3 V ± 10% or 2.5 V ± 5% DDA DDB 1 Symbol Min f — ...
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... Output impedance (single ended) Mismatch in a pair Change in V between “0” and “1” OD Change in V between “0” and “1” OS Output current on short to GND 1 XPADVDDrefers to the SGMII transmitter output supply voltage. MPC8313E PowerQUICC 32 Symbol Min 0.3*XPADVDD OL V RING |V | (XPADVDD/2)/1 ...
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... T Unit Interval fall time (80%–20 fall V rise time (20%–80 rise Source synchronous clock is not supported MPC8313E PowerQUICC Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Symbol Min Max Unit Vrx_diffpp 100 1200 mV Peak to peak input differential Vl 30 100 mV os ...
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... Combined Deterministic J DR and Random Jitter Tolerance Sinusoidal Jitter Tolerance Jsin Total Jitter Tolerance J T Bit Error Ratio BER Unit Interval UI Vrx_diffpp_max/2 Vrx_diffpp_min/2 –Vrx_diffpp_min/2 –Vrx_diffpp_max/2 MPC8313E PowerQUICC 34 Min Max 0.37 0.55 0.1 0.65 -12 10 800 800 0 0 .275 .4 Time (UI) Figure 16. Receive Input Compliance Mask ™ ...
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... USB clock reference (K) goes high (H). Also, t symbolizes us timing (USB) for the USB clock reference ( high (H), with respect to the output (O) going invalid (X) or output hold time. MPC8313E PowerQUICC Freescale Semiconductor Table 36. USB DC Electrical Characteristics ...
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... Figure 17 Figure 18 provide the AC test load and signals for the USB, respectively. and Output USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: 9.2 On-Chip USB PHY See chapter 7 in the USB Specifications Rev 2.0 MPC8313E PowerQUICC Ω Ω Figure 17. USB AC Test Load t USIVKH ...
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... Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) MPC8313E PowerQUICC Freescale Semiconductor Symbol Min V ...
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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 19 provides the AC test load for the local bus. Output MPC8313E PowerQUICC 38 1 Symbol t LBKHOV ...
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... Figure 22 show the local bus signals. LCLK[n] Input Signals: LAD[0:15] Input Signal: LGTA Output Signals: LBCTL/LBCKE/LOE/ Output Signals: LAD[0:15] LALE Figure 20. Local Bus Signals, Non-Special Signals Only MPC8313E PowerQUICC Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT ™ II Pro Processor Hardware Specifications, Rev. 0 ...
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... Local Bus LCLK T1 T3 GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8313E PowerQUICC 40 t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ t LBKHOV ™ ...
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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8313E PowerQUICC Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ t LBKHOV ™ ...
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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8313E PowerQUICC 42 Symbol Condition – ...
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... Figure 23. AC Test Load for the JTAG Interface Figure 24 provides the JTAG clock input timing diagram. JTAG External Clock Figure 24. JTAG Clock Input Timing Diagram Figure 25 provides the TRST timing diagram. TRST MPC8313E PowerQUICC Freescale Semiconductor Table 2). 2 Symbol t JTKLDZ t TDO ...
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... Output Data Valid Data Outputs Figure 27 provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 27. Test Access Port Timing Diagram MPC8313E PowerQUICC JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (NV DD Figure 26. Boundary-Scan Timing Diagram VM ...
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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8313E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used. 4. I/O pins will obstruct the SDA and SCL lines ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. The MPC8313E provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...
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... Figure 29 shows the AC timing diagram for the I SDA t I2CF t I2CL SCL t I2SXKL S MPC8313E PowerQUICC Freescale Semiconductor 2 C bus I2DVKH I2KHKL t I2SXKL t t I2CH I2SVKH t I2DXKL Sr 2 Figure 29 Bus AC Timing Diagram ™ II Pro Processor Hardware Specifications, Rev I2CF ...
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... PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8313E is configured as a host or agent device. Table 45 shows the PCI AC timing specifications at 66 MHz. ...
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... Input timings are measured at the pin. Figure 30 provides the AC test load for PCI. Output Figure 31 shows the PCI input AC timing conditions. CLK Input Figure 31. PCI Input AC Timing Measurement Conditions MPC8313E PowerQUICC Freescale Semiconductor 1 Symbol Min t — PCKHOV t 2 ...
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... PCI Figure 32 shows the PCI output AC timing conditions. CLK Output Delay High-Impedance Output Figure 32. PCI Output AC Timing Measurement Condition MPC8313E PowerQUICC 50 t PCKHOV t PCKHOX t PCKHOZ ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...
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... Timers This section describes the DC and AC electrical specifications for the timers. 14.1 Timers DC Electrical Characteristics Table 47 provides the DC electrical characteristics for the MPC8313E timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 47. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...
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... GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least t Figure 34 provides the AC test load for the GPIO. Output MPC8313E PowerQUICC 52 Symbol Condition – ...
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... Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t in edge triggered mode. MPC8313E PowerQUICC Freescale Semiconductor Table 51. IPIC DC Electrical Characteristics Symbol ...
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... SPI 17 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8313E 17.1 SPI DC Electrical Characteristics Table 53 provides the DC electrical characteristics for the MPC8313E SPI. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 17 ...
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... SPI timing in Master mode (internal clock). SPICLK (output) Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8313E PowerQUICC Freescale Semiconductor = 50 Ω Figure 35. SPI AC Test Load Table t NEIXKH ...
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... Package and Pin Listings 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8313E is available in a thermally enhanced plastic ball grid array (TEPBGAII), see MPC8313E TEPBGAII,” and Section 18.2, “Mechanical Dimensions of the MPC8313E TEPBGAII,” information on the TEPBGAII. ...
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... Figure 38. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8313E TEPBGAII 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5. Package code 5368 is to account for PGE and the built–in heat spreader. ...
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... Package and Pin Listings 18.3 Pinout Listings Table 55 provides the pin-out listing for the MPC8313E, TEPBGAII package. Table 55. MPC8313E TEPBGAII Pinout Listing Signal MEMC_MDQ[0] MEMC_MDQ[1] MEMC_MDQ[2] MEMC_MDQ[3] MEMC_MDQ[4] MEMC_MDQ[5] MEMC_MDQ[6] MEMC_MDQ[7] MEMC_MDQ[8] MEMC_MDQ[9] MEMC_MDQ[10] MEMC_MDQ[11] MEMC_MDQ[12] MEMC_MDQ[13] MEMC_MDQ[14] MEMC_MDQ[15] MEMC_MDQ[16] MEMC_MDQ[17] MEMC_MDQ[18] ...
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... Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal MEMC_MDQ[30] MEMC_MDQ[31] MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MDQS[2] MEMC_MDQS[3] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS[0] MEMC_MCS[1] MEMC_MCKE ...
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... Package and Pin Listings Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal MEMC_MCK MEMC_MCK MEMC_MODT[0] MEMC_MODT[1] LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LA24 LA25 ...
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... Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal LCS[3] LWE[0] LWE[1] LBCTL LALE/M1LALE/M2LALE LGPL0 LGPL1 LGPL2 LGPL3 LGPL4 LGPL5 LCLK0 LCLK1 LA0/GPIO[0] LA1/GPIO[1] LA2/GPIO[2] LA3/GPIO[3] LA4/GPIO[4] LA5/GPIO[5] LA6/GPIO[6] LA7/GPIO[7] LA8/GPIO[13] LA9/GPIO[14] LA10 LA11 LA12 LA13 LA14 LA15 UART_SOUT1/MSRCID0 UART_SIN1/MSRCID1 UART_CTS[1]/GPIO[8]/MSRCID2 ...
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... Package and Pin Listings Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal UART_SOUT2/MSRCID4 UART_SIN2/MDVAL UART_CTS[2] UART_RTS[2] IIC1_SDA/CKSTOP_OUT IIC1_SCL/CKSTOP_IN IIC2_SDA/PMC_PWR_OK/GPIO[10] IIC2_SCL/GPIO[11] MCP_OUT IRQ[0]/MCP_IN IRQ[1] IRQ[2] IRQ[3] /CKSTOP_OUT IRQ[4]/ CKSTOP_IN/GPIO[12] CFG_CLKIN_DIV EXT_PWR_CTRL CFG_LBIU_MUX_EN TCK TDI TDO TMS TRST TEST_MODE QUIESCE HRESET MPC8313E PowerQUICC ...
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... Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal PORESET SRESET SYS_CR_CLK_IN SYS_CR_CLK_OUT SYS_CLK_IN USB_CR_CLK_IN USB_CR_CLK_OUT USB_CLK_IN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN AV DD1 AV DD2 PCI_INTA PCI_RESET_OUT PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] MPC8313E PowerQUICC Freescale Semiconductor Package Pin Number ...
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... Package and Pin Listings Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_C/BE[0] PCI_C/BE[1] PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR ...
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... Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 PCI_PME TSEC1_COL/USBDR_TXDRXD0 TSEC1_CRS/USBDR_TXDRXD1 TSEC1_GTX_CLK/USBDR_TXDRXD2 TSEC1_RX_CLK/USBDR_TXDRXD3 TSCE1_RX_DV/USBDR_TXDRXD4 TSEC1_RXD[3]/USBDR_TXDRXD5 TSEC1_RXD[2]/USBDR_TXDRXD6 TSEC1_RXD[1]/USBDR_TXDRXD7 TSEC1_RXD[0]/USBDR_NXT/TSEC_1588_TRIG1 TSEC1_RX_ER/USBDR_DIR/TESC_1588_TRIG2 TSEC1_TX_CLK/USBDR_CLK/TSEC_1588_CLK TSEC1_TXD[3]/TSEC_1588_GCLK TSEC1_TXD[2]/TSEC_1588_PP1 TSEC1_TXD[1]/TSEC_1588_PP2 TSEC1_TXD[0]/USBDR_STP/TSEC_1588_PP3 TSEC1_TX_EN/TSEC_1588_ALARM1 TSEC1_TX_ER/TSEC_1588_ALARM2 TSEC1_GTX_CLK125 ...
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... Package and Pin Listings Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal TSCE2_RX_DV/GTM1_TGATE2/GTM2_TGATE1/GPIO[19] TSEC2_RXD[3]/GPIO[20] TSEC2_RXD[2]/GPIO[21] TSEC2_RXD[1]/GPIO[22] TSEC2_RXD[0]/GPIO[23] TSEC2_RX_ER/GTM1_TOUT2/GTM2_TOUT1/GPIO[24] TSEC2_TX_CLK/GPIO[25] TSEC2_TXD[3]/CFG_RESET_SOURCE[0] TSEC2_TXD[2]/CFG_RESET_SOURCE[1] TSEC2_TXD[1]/CFG_RESET_SOURCE[2] TSEC2_TXD[0]/CFG_RESET_SOURCE[3] TSEC2_TX_EN/GPIO[26] TSEC2_TX_ER/GPIO[27] TXA TXA RXA RXA TXB TXB RXB RXB SD_IMP_CAL_RX ...
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... Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal USB_TPA USB_RBIAS USB_PLL_PWR3 USB_PLL_GND USB_PLL_PWR1 USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA USBDR_DRIVE_VBUS/GTM1_TIN1/GTM2_TIN2 USBDR_PWRFAULT/GTM1_TGATE1/GTM2_TGATE2 USBDR_PCTL0/GTM1_TOUT1 USBDR_PCTL1 SPIMOSI/GTM1_TIN3/GTM2_TIN4/GPIO[28] SPIMISO/GTM1_TGATE3/GTM2_TGATE4/GPIO[29]/LDVAL SPICLK/GTM1_TOUT3/GPIO[30] SPISEL/GPIO[31 DDA LV DDB MV REF NV DD MPC8313E PowerQUICC Freescale Semiconductor Package Pin Number L26 M24 M26 ...
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... Package and Pin Listings Table 55. MPC8313E TEPBGAII Pinout Listing (continued) Signal DDC VSS Notes: 1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin ...
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... Clocking Figure 39 shows the internal distribution of clocks within the MPC8313E. MPC8313E USB Mac USB PHY PLL mux USB_CLK_IN USB_CR_CLK_IN Crystal /1,/2 USB_CR_CLK_OUT CFG_CLKIN _DIV SYS_CLK_IN SYS_CR_CLK_IN Crystal SYS_CR_CLK_OUT eTSEC GTX_CLK125 125-MHz source Protocol Converter 1 Multiplication factor 1.5, 2, 2.5, and 3. 2 Multiplication factor and 6. Value is decided by RCWLR[SPMF]. ...
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... Clocking The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI clock divider (÷ ...
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... TSEC1 TSEC2 Security Core, I2C, SAP, TPR USB DR PCI and DMA complex Table 57 provides the operating frequencies for the MPC8313E TEPBGA II under recommended operating conditions (see Table Table 57. Operating Frequencies for TEPBGA I I Characteristic e300 core frequency ( core_clk ) Coherent system bus frequency ...
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... High 0011 High 0100 High 0101 High 0110 Low 0010 Low 0011 Low 0100 MPC8313E PowerQUICC 72 Table 58. System PLL Multiplication Factors System PLL Multiplication RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111–1111 Table 59. CSB Frequency Options csb_clk : Input Clock ...
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... MPC8313E PowerQUICC Freescale Semiconductor csb_clk : Input Clock 2 Ratio 120 144 shows the encodings for RCWL[COREPLL]. COREPLL values that are NOTE Table 60. e300 Core PLL Configuration core_clk : csb_clk Ratio PLL bypassed ...
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... MPC8313E PowerQUICC 74 core_clk : csb_clk Ratio 2.5:1 3:1 3:1 3:1 Table 61. System Clock Frequencies LBC(lbc_clk) CSB(csb_ DDR /2 /4 clk) (ddr_clk) 144.0 288.0 36 120.0 240 150.0 300.0 37.5 18.8 125.0 250.0 62.5 31.25 15.6 160.0 320.0 40 128 ...
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... APLL VCO operating range of 400-800 MHz must not be violated. Note 3: csb_clk frequencies of less than 133MHz will not support Gigabit Ethernet data rates. 1 System PLL Multiplication Factor 2 System PLL VCO Divider 3 Frequency of USB PLL Input reference MPC8313E PowerQUICC Freescale Semiconductor 133.3 266.7 66.7 33.34 16.7 ™ II Pro Processor Hardware Specifications, Rev. 0 Clocking Note 1 133 ...
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... Thermal 20 Thermal This section describes the thermal specifications of the MPC8313E. 20.1 Thermal Characteristics provides the package thermal characteristics for the 516 27 × TEPBGAII. Table 62 Table 62. Package Thermal Characteristics for TEPBGAII Characteristic Junction to Ambient Natural Convection Junction to Ambient Natural Convection Junction to Ambient (@200 ft/min) ...
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... D When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8313E PowerQUICC Freescale Semiconductor where P ...
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... The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8313E PowerQUICC 78 Ψ ) can be used to determine the junction temperature with a JT × ...
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... Table 63. Heat Sinks and Junction-to-Case Thermal Resistance of MPC8313E (TEPBGAII) Heat Sink Assuming Thermal Grease AAVID 30x30x9.4 mm Pin Fin AAVID 30x30x9.4 mm Pin Fin AAVID 30x30x9.4 mm Pin Fin AAVID 31x35x23 mm Pin Fin AAVID 31x35x23 mm Pin Fin AAVID 31x35x23 mm Pin Fin Wakefield, 53x53x25 mm Pin Fin ...
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... Such peeling forces reduce the solder joint lifetime of the package. Recommended maximum force on the top of the package (4.5 kg) force adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. MPC8313E PowerQUICC 80 408-436-8770 800-522-6752 ...
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... This section provides electrical and thermal design recommendations for successful application of the MPC8313E SYS_CLK_IN 21.1 System Clocking The MPC8313E includes two PLLs. 1. The platform PLL (AV DD2 SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio configuration bits as described in 2 ...
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... Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8313E system, and the MPC8313E itself requires a clean, tightly regulated source of power. Therefore recommended that ...
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... VSS pins of the device. 21.5 Output Buffer DC Impedance The MPC8313E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I To measure Z for the single-ended drivers, an external resistor is connected from the chip pad VSS ...
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... Configuration Pin Muxing The MPC8313E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...
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... IC). Regardless of the numbering, the signal placement recommended in Figure 42 is common to all known emulators. MPC8313E PowerQUICC Freescale Semiconductor allows the COP to independently assert HRESET or TRST, while adds many benefits—breakpoints, watchpoints, register and memory Figure ™ ...
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... Some systems require power to be fed from the application board into the debugger repeater card via the COP header. In this case the resistor value for VDD_SENSE should be around 20Ω. 2. Key location; pin 14 is not physically present on the COP header. MPC8313E PowerQUICC 86 PORESET ...
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... Part Numbers Fully Addressed by This Document Table 66 provides the Freescale part numbering nomenclature for the MPC8313E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions ...
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... Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8313EEC Rev. 0 06/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...