mpc8313e Freescale Semiconductor, Inc, mpc8313e Datasheet - Page 82

• Manufacturer Part Number: mpc8313e
• Description: Mpc8313e Powerquicc Ii Pro Processor
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
Figure 40
21.3
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8313E system, and the
MPC8313E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each V
and LV
NV
minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern.
Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS
tantalum or Sanyo OSCON).
21.4
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to NV
Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain
unconnected.
82
DD
, GV
DDB
Connection Recommendations
Decoupling Recommendations
shows the PLL power supply filter circuit.
DD
pins of the device. These decoupling capacitors should receive their power from separate V
DD
, LV
, NV
DD
MPC8313E PowerQUICC
V
DD
, LV
DD
, GV
DDA
DD
, LV
Figure 40. PLL Power Supply Filter Circuit
, LV
10 Ω
DDB
DD
and VSS power planes in the PCB, utilizing short traces to
, LV
™
2.2 µF
II Pro Processor Hardware Specifications, Rev. 0
DDA
, and LV
VSS
DD
Low ESL Surface Mount Capacitors
, GV
DDB
2.2 µF
DD
planes, to enable quick recharging of the
, LV
DD
DD
AV
DD
DD
, LV
pin being supplied to minimize
, NV
(or L2AV
DDA
DD
, GV
or LV
DD
)
Freescale Semiconductor
DD
DDB
, LV
as required.
DD
, LV
DDA
DD
DD
,
,