mpc8308 Freescale Semiconductor, Inc, mpc8308 Datasheet - Page 77

• Manufacturer Part Number: mpc8308
• Description: Mpc8308 Powerquicc Ii Pro Processor Hardware Specification
• Manufacturer: Freescale Semiconductor, Inc

Table 55
(Table
21.2
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
Freescale Semiconductor
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR2 memory bus frequency (MCK)
Local bus frequency (LCLK 0 )
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk ,
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x
MCK, LCLK0, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
the csb_clk frequency (depending on RCWL[LBCM]).
2).
provides the operating frequencies for the device under recommended operating conditions
System PLL Configuration
Section 21, “Clocking,”
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Characteristic
3
RCWL[SPMF]
0110–1111
Table 55. Operating Frequencies for MPC8308
0000
0001
0010
0011
0100
0101
2
1
Table 56. System PLL Ratio
the LBCM, DDRCM, and SPMF parameters in the reset
csb_clk : SYS_CLK_IN
Reserved
Reserved
Reserved
Maximum Operating Frequency
2 : 1
3 : 1
4 : 1
5 : 1
Table 56
400
133
133
66
shows the multiplication factor
MHz
MHz
MHz
MHz
Unit
Clocking
77