mpc89x54a Megawin Technology, mpc89x54a Datasheet
mpc89x54a
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mpc89x54a Summary of contents
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... DC Characteristics (MPC89L54A)...................................................................................... 35 Package Dimension.............................................................................................................. 36 Revision History .................................................................................................................. 39 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2004 All right reserved. MPC89x54A 8-bit micro-controller 2007/12 version A11 MEGAWIN ...
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... MPC89L54A, minimum 2.7V requirement in flash write operation (ISP/ICP/…...) - Built-in Low-Voltage-Reset circuit. Operating Temperature - Industrial (-40°C to +85°C)* Maximum Operating Frequency: - Optional 12T or 6T mode - Up to 48MHz@12T or 24MHz@6T, Industrial range Three package types: - PDIP 40: MPC89x54AE - PLCC 44: MPC89x54AP - PQFP 44: MPC89x54AF 2 MPC89x54A Data Sheet MEGAWIN ...
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... Tested by sampling MEGAWIN MPC89x54A Data Sheet 3 ...
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... The user can configure the device to run in 12 clocks per machine cycle clocks per machine cycle to achieve twice performance. MPC89x54A is built with four 8-bit I/O ports, one 4-bit I/O ports, three 16-bit timer/counters, an eight-source, four-priority-level interrupt structure, an enhanced UART, and on-chip crystal oscillator ...
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... BU General-purposed I/O with weak pull-up resistance inside. When 1s are written 7 into Port1, the strong output driving 8 PMOS only turn-on two clock periods 9 and then the weak pull-up resistance 10 MPC89x54A Data Sheet Description also used as one of emits the high-order during accessing ...
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... EA must be kept at low to enable the device to fetch program code from external flash memory. An internal pull-up resistance has been embedded in this pin Input to the inverting oscillator amplifier Output from the inverting amplifier Power Supply 16 G Ground MPC89x54A Data Sheet MEGAWIN ...
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... MPC89x54AF (PQFP-44 MPC89x54A Data Sheet P0.4 (AD4) 38 P0.5 (AD5) 37 P0.6 (AD6) 36 P0.7 (AD7) 35 /EA MPC89x54AP 34 P4.1 (PLCC-44) 33 ALE 32 /PSEN 31 P2.7 (A15) 30 P2.6 (A14 ...
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... Port2 Latch Port0 Latch RAM 256 Stack Pointer TMP1 Timer 0/1 Timer 2 ALU UART WDT Port1 Latch Port3 Latch Port4 Latch Port1 Driver Port3 Driver Port4 Driver P1.0 ~ P1.7 P3.0 ~ P3.7 P4.0 ~ P4.3 MPC89X54A Block Diagram MPC89x54A Data Sheet Flash ROM ISP Address Generator Program Counter DPTR ERAM MEGAWIN ...
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... TF2 EXF2 RCLK TCLK EXEN2 TR2 RS1 RS0 - - ENW CLW WIDL - - - - - ISPEN BS SRST - - - - - - EBH MPC89x54A Data Sheet IFMT SCMD ISPCR TH2 IPH TH1 AUXR PCON INITIAL VALUE 11111111B 00000111B 00000000B 00000000B GF0 PD IDL 01110000B IT1 IE0 IT0 00000000B C// 00000000B ...
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... Memory Organization Address Space for MPC89x54A RAM Address Space for MPC89x54A Embedded Flash Memory Bit-7 Bit-6 Bit-5 ISPAS1 FZWDTCR 10 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, Access it via indirect addressing 0000-03FF on-chip expanded RAM (1024B), ...
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... Nonvolatile Registers: There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to configure the MPC89x54A options. Generally these two nonvolatile registers will be written via a popular NVM writer, i.e., Hi-Lo System All-11, Leaper-48 and Megawin-Provided MCU writer. Furthermore, the user can change the NVM register OR1 by the ISP program in a manner as same as writing the data flash, but OR0 can only be written via an off-line popular NVM writer ...
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... The gained of crystal oscillator is enough for oscillator to start oscillating MHz. HWBS: Used to configure the MPC89x54A boot from ISP program or normal application program after the power-on sequence. 0:= The MPC89x54A will boot from ISP start address after power-on. ...
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... The leading 16 K bytes flash memory is designed for storage of the user program, and followed 47 K bytes flash memory is shared with nonvolatile data flash and ISP program. While the program counter of MPC89x54A is spanning over 3FFFh, the device will fetch its program code from the external memory at once ignoring the /EA pin status. In that case, it will never fetch the program code from the following embedded flash ...
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... Functional Description TIMERS/COUNTERS MPC89x54A has three 16-bit timers, and they are named T0, T1 and T2. Each of them can also be used as a general event counter, which counts the transition from While T0/T1/T2 is used as “timer” function, the time unit that used to measure the timer is machine cycle ...
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... EXEN2=0 causes Timer2 to ignore events at T2EX. TR2: Start/Stop control for Timer2. MEGAWIN Bit-4 Bit-3 Bit-2 Bit-1 TR0 IE1 IT1 IE0 Bit-4 Bit-3 Bit-2 Bit-1 T2OE Bit-4 Bit-3 Bit-2 Bit-1 TCLK EXEN2 TR2 C//T2 MPC89x54A Data Sheet Bit-0 IT0 Bit-0 DCEN Bit-0 CP/RL2 15 ...
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... TLx does not only set TFx, but also reloads TLx with the content of THx, which is determined by user’s program. The reload leaves THx unchanged. Mode 2 operation is the same for Timer0 and Timer1 TLx[4:0] THx[7: TLx[7:0] THx[7:0] 1 MPC89x54A Data Sheet TFx Interrupt Mode 0 TFx Interrupt Mode 1 MEGAWIN ...
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... MEGAWIN 0 TLx [7:0] 1 THx [7:0] 0 TL0 [7: TH0 [7:0] 1 TR2 DCEN 0 x OFF 1 0 Baud-Rate Generation 1 0 Capture 1 0 Auto-Reload Up-only 1 1 Auto-Reload Up/Down Timer2 Mode Table MPC89x54A Data Sheet Interrupt TFx Reload Mode 2 Interrupt TF0 Mode 3 Interrupt TF1 Mode 17 ...
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... Timer2 is also can be configured as a periodical signal generator. The MPC89x54A is able to generate a programmable clock output on P1.0. When T2OE bit is set and C//T2 bit is cleared, Timer2 overflow pulse will generate a 50% duty clock and output that to P1.0. The frequency of clock-out is calculated according to the following formula. ...
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... Timer2 and if counting direction is UP, the overflow loads RCAP2H, RCAP2L contents onto Timer2 OSC/ pin 1 C//T2 TR2 MEGAWIN 0 TL2 [7:0] TH2[7:0] 1 RCAP2L [7:0] RCAP2H [7:0] FFH FFH TL2 [7:0] TH2[7:0] RCAP2L [7:0] RCAP2H [7:0] MPC89x54A Data Sheet TF2 Interrupt EXF2 EXF2 TF2 Interrupt T2EX pin 19 ...
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... T2 pin C//T2 TR2 T2EX pin EXEN2 20 16 Oscillator Frequency TL2[7:0] TH2[7:0] RCAP2L[7:0] RCAP2H[7:0] EXF2 Timer2 interrupt MPC89x54A Data Sheet (counting T2EX) (as a timer) Timer1 overflow 2 “0” “1” SMOD “1” “0” RCLK 16 “1” “0” TCLK RX Clock ...
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... Interrupt There are eight interrupt sources available in MPC89x54A. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit (EA), which can be cleared to disable all interrupts at once. Each interrupt source has two corresponding bits to represent its priority. One is located in SFR named IPH and the other in IP/XICON register ...
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... PT0H: If set, Set priority for timer0 interrupt highest PX0H: If set, Set priority for external interrupt 0 highest 22 Bit-4 Bit-3 Bit-2 ES ET1 EX1 Bit-4 Bit-3 Bit-2 PS PT1 PX1 Bit-4 Bit-3 Bit-2 PSH PT1H PX1H MPC89x54A Data Sheet Bit-1 Bit-0 ET0 EX0 Bit-1 Bit-0 PT0 PX0 Bit-1 Bit-0 PT0H PX0H MEGAWIN ...
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... Interrupt 2 types control bit. Set/Cleared by software to specify falling edge/low level triggered interrupt. Watchdog Timer CLK/12 ENW 8-bit pre-scalar timer IDLE WIDL CLRW MEGAWIN Priority Level 1 (highest Bit-4 Bit-3 Bit-2 IT3 PX2 EX2 8 PS0 PS1 PS2 MPC89x54A Data Sheet Bit-1 Bit-0 IE2 IT2 15-bit WDT RESET 23 ...
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... Serial IO Port (UART) The serial port of MPC89x54A is duplex. It can transmit and receive simultaneously. The receiving and transmitting of the serial port share the same SFR SBUF, but actually there are two SBUF registers implemented in the chip, one is for transmitting and the other is for receiving ...
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... Mode set the serial port operate under Mode 3 MEGAWIN SMOD SMOD (Timer-1 overflow rate) 32 (Timer-2 overflow rate Bit-4 Bit-3 Bit-2 REN TB8 RB8 MPC89x54A Data Sheet osc Bit-1 Bit ...
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... RI in SFR SCON. Normally, an UART will set bit RI whenever it has done a byte reception; but for the UART in the MPC89x54A, if the bit SM2 is set, it will set RI according to the following formula (SM2 == 1) && (SBUF == Compared Byte) && (RB8 == 1) ...
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... Any positive pulse from RESET pin must be kept at least two-machine cycle, or the device cannot be reset. Power Saving Mode and POF There are two power saving modes which are selectable to drive the MPC89x54A to enter power-saving mode. 1. IDLE mode The user can set the bit PCON.0 to drive this chip entering IDLE mode. ...
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... Unlike RAM’s real-time operation, to erase flash or to write (program) flash often takes longer 28 ALE PSEN Port0 1 1 Data 1 1 Float 0 0 Data 0 0 Float MPC89x54A Data Sheet Port1 Port2 Port3 Data Data Data Data Address Data Data Data Data Data Data Data MEGAWIN ...
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... Furthermore quite complex timing procedure to erase/program flash. Fortunately, the MPC89x54A carried with convenient mechanism to help the user read/change the flash content. Just filling the target address and data into several SFR, and triggering the built-in ISP automation, the user can easily erase, read, and program the embedded flash and option registers OR1 ...
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... SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if ISPCR ISP activity will be triggered. When this register is read, the device ID of MPC89x54A will be returned (2 bytes). The MSB byte of DID is F1h and LSB byte 04h. IFADRL[0] is used to select HIGH/LOW byte of DID. ...
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... SCMD ← B9h (CPU progressing will be hold here) (CPU continues and currently IFD contain the desired data byte ) Booting Program Entrance The MPC89x54A boots according to the following rule HWBS == 0 ) System will boot from ISP program else System will boot from normal AP program Above rule is adaptive only for power-up procedure, while not software reset ...
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... Note : Even the users do not need ISP space, the OR0[5:4] still needs to be programmed with {10} if IAP data flash is desired. In other words, the maximum available size in data flash for IAP operation is 46K bytes MPC89x54A Data Sheet MEGAWIN ...
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... ALE is active only during access to external memory for both MOVC and MOVX SFR: AUXR1 Bit-7 Bit-6 Bit GF2: General purpose flag DPS: Data pointer switch 0: = Make the data pointer-0 active 1: = Make the data pointer-1 active MEGAWIN Bit-4 Bit-3 Bit Bit-4 Bit-3 Bit-2 - GF2 - MPC89x54A Data Sheet Bit-1 Bit-0 ERAM AO Bit-1 Bit-0 - DPS 33 ...
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... Logic transition current (P1,2,3, Operating current @20MHz CC I Idle mode current @ 20MHz IDLE I Power down current PD Rrst Internal pull-down resistance in RESET 34 (MPC89E54A) -0.5 ~ VCC + 0.5 Parameter MPC89x54A Data Sheet Rating Unit °C -55 ~ +125 °C - 150 V -0.5 ~ +6.0 V 500 Specification Test Condition Min. ...
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... Idle mode current @ 20MHz IDLE I Power down current PD Rrst Internal pull-down resistance in RESET MEGAWIN (MPC89L54A) -0.3 ~ VCC + 0.3 (MPC89L54A) Parameter (P1, P2, P3, P4) (P0, ALE, PSEN) (P1, P2, P3, P4) (ALE, PSEN) (P1,2,3,4) (P1,2,3,4) MPC89x54A Data Sheet Rating Unit °C -55 ~ +125 °C - 150 V -0.3 ~ +4.2 V 500 Specification Test Condition Min. Typ. Max. 0.8 Vcc=3 ...
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... Package Dimension 40-pin PDIP (MPC89x54AE) 36 MPC89x54A Data Sheet MEGAWIN ...
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... PLCC (MPC89x54AP) MEGAWIN MPC89x54A Data Sheet 37 ...
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... PQFP (MPC89x54AF) 38 MPC89x54A Data Sheet MEGAWIN ...
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... Update PQFP-44 package shape - Modify pin /EA location for PDIP and PLCC package - Modify bits definition for SFR PCON - Absolute Maximum Rating - Revises the possible operating temperature. - Modify the Storage Temperature - Add 2.7V requirement in flash write operation. - Modify Absolute Maximum Rating. MPC89x54A Data Sheet 39 ...