mpc89x58a Megawin Technology, mpc89x58a Datasheet - Page 11

• Manufacturer Part Number: mpc89x58a
• Description: 8-bit Micro-controller
• Manufacturer: Megawin Technology

Nonvolatile Registers:
There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to
configure the MPC89x58A options.
Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo
System All-11, Leaper-48 and Megawin-Provided MCU writer. Furthermore, the user can
change the NVM register OR1 by the ISP program in a manner as same as writing the data
flash, but OR0 can only be written via an off-line popular NVM writer.
NVM register: OR0 (Option Register 0):
{ISPAS1, ISPAS0}: Used to identify the start address for ISP program
MOVCL: Used to determine if MOVC instruction will be disabled.
SB: Used to determine if the program code will be scrambled while it is dumped.
LOCK: Used to determine if the program code will be locked against the popular writer.
Please check file initial Configuration.pdf to get the default value of the OR0.
{0, 0}: = The ISP space is from 0xEC00 to 0xFBFF (4K size).
{0, 1}: = The ISP space is from 0xF400 to 0xFBFF (2K size).
{1, 0}: = The ISP space is from 0xF800 to 0xFBFF (1K size)
{1, 1}: = No ISP space.
These two bits decide where the ISP program locates, and how the ISP program and the data flash
shares the 31K embedded flash.
If the code is locked, all the data dumped from a popular will always show FFh.
MEGAWIN
Bit-7
-
0:= MOVC is conditionally disabled.
1:= MOVC is always available.
0:= Code dump from Writer is scrambled.
1:= Code dump from Writer is transparent.
0:= lock code.
1:= does not lock code
Bit-6
-
ISPAS1
Bit-5
ISPAS0
MPC89x58A Data Sheet
Bit-4
Bit-3
-
MOVCL
Bit-2
Bit-1
SB
LOCK
Bit-0
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