mpc89l515ap Megawin Technology, mpc89l515ap Datasheet
mpc89l515ap
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... DC Characteristics (MPC89L515A).................................................................................... 34 Package Dimension.............................................................................................................. 35 Revision History .................................................................................................................. 38 This document contains information on a new product under development by Megawin. Megawin reserves the right to change or discontinue this product without notice. © Megawin Technology Co., Ltd. 2008 All rights reserved. MPC89x515A 8-bit micro-controller 2008/12 version A13 MEGAWIN ...
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Features 80C51 Central Processing Unit 63KB on-chip program memory ISP capability; optional 1KB/2KB/4KB ISP memory shared with application flash memory. On-Chip 256 bytes scratch-pad RAM and 1024 bytes auxiliary RAM; Be capable of addressing bytes external ...
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General Description MPC89x515A is a single-chip 8-bit microcontroller with the instruction sets fully compatible with industrial-standard 80C51 series microcontroller. There is 63 Kbytes flash memory embedded for application program, which is shared with In-System Programming code. In-System-Programming allows the users ...
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Pin Description Pin Definition Pin Number Pin Name DIP-40 PLCC-44 P0.0 (AD0 P0.1 (AD1 P0.2 (AD2 P0.3 (AD3 P0.4 (AD4 P0.5 (AD5 P0.6 (AD6 P0.7 (AD7) ...
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P4.0 23 P4.1 34 P4.2 (/INT3) 1 P4.3 (/INT2) 12 RESET 9 10 ALE 30 33 /PSEN XTAL1 19 21 XTAL2 18 20 VDD 40 44 VSS 20 22 MEGAWIN P3.2 and P3.3 also act ...
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Pin Configuration 1 (T2) P1.0 40 (T2EX P1.7 33 RESET 9 32 (RXD) P3 (TXD) P3 (INT0) ...
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RAM ADDR Register B Register ACC TMP2 PSW PSEN Control ALE EA Unit RESET XTAL 1 XTAL 2 MC89X515A Block Diagram MEGAWIN P2.0 ~ P2.7 P0.0 ~ P0.7 Port2 Driver Port0 Driver Port2 Latch Port0 Latch RAM 256 Stack Pointer ...
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Special Function Register ACC WDTCR D8 D0 PSW C8 T2CON T2MOD C0 XICON B8 IP SADEN SADDR SCON SBUF TCON TMOD ...
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Organization Address Space for MPC89x515A RAM Address Space for MPC89x515A embedded Flash memory Bit-7 Bit-6 Bit-5 ISPAS1 FZWDTCR MEGAWIN 00-7F RAM, Access it via direct addressing 80-FF SFR, Access it via direct addressing 80-FF indirect on-chip RAM, ...
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Nonvolatile Registers: There are two Nonvolatile Registers named OR0 and OR1 individually. They are designed to configure the MPC89x515A options. Generally these two nonvolatile registers will be written via a popular NVM writer, say Hi-Lo System All-11, Labtool-48 and Megawin-Provided ...
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NVM register: OR1 (Option Register 1): Bit-7 Bit-6 Bit-5 FZWDTCR FZWDTCR: Used to freeze the WDT-controlling register Configure the SFR WDTCR to be reset only via power-up action, not by software reset nor reset from the Watch Dog ...
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Embedded Flash There is totally 63 K byte flash embedded in the MPC89x515A. The embedded flash is shared by the user application program code and the ISP program code. While the program counter of MPC89x515A is spanning over EBFFh/F3FFh/F7FFh/FBFFh, the ...
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Functional Description TIMERS/COUNTERS MPC89x515A has three 16-bit timers, and they are named T0, T1 and T2. Each of them can also be used as a general event counter, which counts the transition from While T0/T1/T2 is used ...
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SFR: TCON Bit-7 Bit-6 Bit-5 TF1 TR1 TF0 TF1: = Timer1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to the interrupt routine, or clearing the bit in software. TR1: = Timer1 run ...
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EXEN2=1. When whether TCLK or RCLK is 1, this bit is ignored and the timer is forced to auto-reload on Timer2 overflow. TIMER0 (T0) AND TIMER1 (T1) Mode 0 The timer register is configured as a 13-bit register. As ...
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OSC/ pin 1 (Sampled) C//T TRx GATE /INTx Mode 3 Timer1 in Mode3 simply holds its count, the effect is the same as setting TR1 = 1. Timer0 in Mode 3 enables TL0 and TH0 as ...
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C//T2 bit is cleared, Timer2 overflow pulse will generate a 50% duty clock and output that to P1.0. The frequency of clock-out is calculated according to the following formula. Oscillator frequency 4 x (65536 – RCAP2H, RCAP2L) In the ...
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Auto-Reload Up-Only Mode (ARUO) In ARUO mode, Timer2 can be configured to count up with a software-defined value to be reloaded. When reset is applied to the DCEN =0 and CP/RL2=0, Timer2 is at ARUO mode. An overflow on Timer2 ...
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Baud-Rate Generator Mode (BRG) Timer2 can be configured to generate various baud-rates. Bit TCLK and/or RCLK in T2CON allow the serial port transmit and receive baud rates to be derived from either Timer1 or Timer2. When TCLK=0, Timer1 is used ...
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Interrupt There are eight interrupt sources available in MPC89x515A. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit (EA), which can ...
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In other words, interrupts or pending interrupts can be generated or canceled in software. The following content describes several SFR related to interrupt mechanism. SFR: IE (Interrupt Enabling): Bit-7 Bit-6 Bit-5 EA ET2 EA: ...
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IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table. {IPH.x , IP. SFR: XICON (External Interrupt Control): Bit-7 Bit-6 Bit-5 PX3 EX3 IE3 PX3 : If set, Set priority ...
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SFR: WDTCR (Watchdog Timer Control): Bit-7 Bit-6 Bit ENW ENW: Enable WDT while it is set. ENW cannot be cleared by firmware enable watchdog timer does not use watchdog timer CLRW: Clear WDT to ...
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Mode2 An 11-bit data is serially transmitted through TXD or received through RXD. The frame data includes a start bit (0), 8 data bits, a programmable 9th bit and a stop bit (1). On transmit, the 9th data bit comes ...
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SM2: Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. ...
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In other words, not all data reception will respond to RI, while specific data does. By setting the SADDR and the SADEN, the user can filter out those data byte that doesn’t like to care. This feature brings great help ...
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The user can set the bit PCON.1 to drive this chip entering POWER-DOWN mode. In the POWER-DOWN mode, the on-chip oscillator is stopped. The contents of on-chip RAM and SFRs are maintained. The power-down mode can be woken-up by either ...
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Furthermore quite complex timing procedure to erase/program flash. Fortunately, the MPC89x515A carried with convenient mechanism to help the user read/change the flash content. Just filling the target address and data into several SFR, and triggering the built-in ...
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SCMD is the command port for triggering ISP activity. If SCMD is filled with sequential 46h, B9h and if ISPCR ISP activity will be triggered. When this register is read, the device ID of MPC89x515A will be returned ...
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IFMT ← xxxxx010 ISPCR ← 100xx010 IFADRH ← (Address high byte) IFADRL ← (Address low byte) IFD ← (byte date to be written into flash) SCMD ← 46h SCMD ← B9h (CPU progressing will be hold here) (CPU continues) IFMT ...
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SWBS 0, and trigger a software reset. After that, the system will be reset (not powered-up), and the system will refer to SWBS to startup from AP program entrance. For power-up procedure, the HWBS will ...
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Note for Other SFR SFR: AUXR Bit-7 Bit-6 Bit ERAM: Define if hide the expanded RAM access to the external RAM 0: = The internal auxiliary RAM access is enabled 1: = The internal auxiliary ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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Absolute Maximum Rating Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VCC with respect to Ground Maximum total current through VCC and Ground Maximum output current sunk ...
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Package Dimension 40-pin PDIP (MPC89x515AE) MEGAWIN MPC89x515A Data Sheet 35 ...
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PLCC (MPC89x515AP) 36 MPC89x515A Data Sheet MEGAWIN ...
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PQFP (MPC89x515AF) MEGAWIN MPC89x515A Data Sheet 37 ...
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Revision History Version Date Page A3 2004/10 A4 2004/11 P27 A5 2005/01 A6 2005/01 A8 2005/6/14 P5 2005/08 P9 A10 2006/08 P33, 34 A11 2007/03 P33 A12 2007/12 P2 P34, 35 A13 2008/12 38 Description - reorganized ...