mpc5645s Freescale Semiconductor, Inc, mpc5645s Datasheet - Page 12

• Manufacturer Part Number: mpc5645s
• Description: Mpc5645s Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.3.8
The MPC5645S microcontroller has the following flash memory features:
1.3.9
The MPC5645S microcontroller has 64 KB general-purpose on-chip SRAM with the following features:
1.3.10
The MPC5645S microcontroller has 1 MB on-chip graphics SRAM with the following features:
1.3.11
The MPU features the following:
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2 MB of flash memory
— Typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 125 MHz
— Two 4128-bit page buffers with programmable prefetch control
— 64-bit ECC with single-bit correction, double-bit detection for data integrity
Small block flash arrangement to support features such as boot block, EEPROM Emulation, operating system block
— 816 KB
— 264 KB
— 2128 KB
— 6256 KB
Hardware managed flash writes, erase and verify sequence
Censorship protection scheme to prevent Flash content visibility
Typical SRAM access time: 1 wait-state for reads and 32-bit writes
32-bit ECC with single-bit correction, double bit detection for data integrity
Supports byte (8-bit), half word (16-bit), word (32-bit), and double-word (64-bit) writes for optimal use of memory
User transparent ECC encoding and decoding for byte, half word, and word accesses
Separate internal power domains applied to 56 KB and 8 KB SRAM blocks during STANDBY modes to retain
contents during low power mode
Two crossbar slave ports:
— One dedicated to the 2D Graphics Accelerator (GFX2D) access
— One dedicated to all other crossbar masters
Usable as general purpose SRAM
Supports byte (8-bit), half word (16-bit), word (32-bit), and double-word (64-bit) writes for optimal use of memory
RAM controller with hardware RAM fill function supporting all-zeroes or all-ones SRAM initialization
Independent data buffers (one per AHB port) for maximum system performance
— Optimized for burst transfers (read + write)
— Programmable read prefetch capabilities
Sixteen region descriptors for per master protection
Start and end address defined with 32-byte granularity
– One set of page buffers can be allocated for code-only, fixed partitions of code and data, all available for any
– One set of page buffers allocated to Display Controller Units, Graphics Accelerator, and the eDMA
On-chip flash memory with ECC
SRAM
On-chip graphics SRAM
Memory Protection Unit (MPU)
access
MPC5645S Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor