mpc5566 Freescale Semiconductor, Inc, mpc5566 Datasheet - Page 62

• Manufacturer Part Number: mpc5566
• Description: Mpc5566 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Revision History for the MPC5566 Data Sheet
62
Location
Table
Table
Table 24,
Table
Figure
Table
22, Bus Operation Timing:
23, External Interrupt Timing:
25, eMIOS Timing:
26, DSPI Timing:
17, eMIOS Timing: Added figure.
eTPU Timing
• Added a column to the table for 72 MHz minimum and maximum bus frequencies.
• Spec 1: 72 MHz Min. column = 13.3.
• Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
• Specs 5, and 6: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
• Spec 5: EBI and Calibration sections, 72 MHz Min column, EBTS = 0 is 1.0, EBTS = 1 is 1.5.
• Spec 6: EBI section, 72 MHz Max column, EBTS = 0 is 5.0, EBTS = 1 is 6.0.
• Spec 6a: Calibration section, 72 MHz Max column, EBTS = 0 is 6.0, EBTS = 1 is 7.0
• Specs 7 and 8: Added the BB signal for arbitration. Added the following calibration signals: CAL_ADDR[9:30],
• Footnote 1: Deleted ‘. . F
• Deleted second figure after table ‘External Interrupt Setup Timing.’
• Footnote 1: Deleted ‘. . .F
• Deleted second figure, ‘eTPU Input/Output Timing’ after this table.
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
• Deleted (MTS) from the heading, table, and footnotes.
• Footnote 1: Deleted ‘. . .F
• Added Footnote 2: ‘This specification does not include the rise and fall times. When calculating the minimum
• Added 144 MHz column to the table.
• Spec1:SCK Cycle Time: changes to values: 80 MHz, min. = 24.4; 112 MHz, min. = 17.5, max = 2.1;
• Spec1:SCK Cycle Time: Added footnote 4 to the 144 MHz min. and max values that reads: Preliminary.
• Spec 2, PCS to SCK delay, 144 MHz, min. TBD
• Spec 3, After SCK delay, 144 MHz, min. TBD
• Spec 9, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Spec 10, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Spec 11, Master (MTFE = 1, CPHA = 0), 144 MHz, max TBD
• Spec 12, Master (MTFE = 1, CPHA = 0), 144 MHz, min. TBD
• Added to beginning of footnote 1 ‘All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad
• Footnote 1: Deleted ‘V
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
CAL_CS[0:3], CAL_DATA[0:15], CAL_OE, CAL_RD_WR, CAL_TS, CAL_WE/BE[0:1].
CAL_DATA[0:15], CAL_RD_WR, CAL_TS.
0b11.’
SRC = 0b11.’
eTPU pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
SRC = 0b11.’
eMIOS pulse width, include the rise and fall times defined in the slew rate control fields (SRC) of the pad
configuration registers (PCR).’
132 MHz, min. = 14.8, max = 1.8; 144 MHz, min. = 13.6, max = 1.6.
Specification pending final characterization
type M or MH. DSPI signals using pad types of S or SH have an additional delay based on the slew rate.’
Table 33. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
DD
MPC5566 Microcontroller Data Sheet, Rev. 2.0
SYS
SYS
SYS
= 1.35–1.65 V’ and ‘V
= 132 MHz’, ‘V
= 132 MHz’, ‘V
= 132 MHz, ‘V
Description of Changes
DD33
DD33
DD33
DD33
and V
and V
and V
and V
DDSYN
DDSYN
DDSYN
DDSYN
= 3.0–3.6 V’ and ‘ .and CL = 200 pF with SRC =
= 3.0–3.6 V’ and ‘and CL = 200 pF with
= 3.0–3.6 V’ and ‘and CL = 200 pF with
= 3.0–3.6 V.
Freescale Semiconductor