mpc5561 Freescale Semiconductor, Inc, mpc5561 Datasheet - Page 10

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mpc5561

Manufacturer Part Number
mpc5561
Description
Mpc5561 Power Architecture Tm 32-bit Mcu For Automotive
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Features
2.6.10
2.6.11
2.6.12
2.6.13
10
Hardware read-while-write feature that can erase/program blocks while other blocks are read (used
for EEPROM emulation and data calibration)
12 blocks with sizes ranging from 16–128 KB to support features such as boot block, operating
system block, and EEPROM emulation. Blocks are structured as follows:
— 2 x 16 KB
— 2 x 48 KB
— 2 x 64 KB
— 6 x 128 KB
Read while write with multiple partitions
Parallel programming mode to support rapid end of line programming
Hardware programming state machine
Four-way or eight-way set-associative unified (instruction and data) cache
— Two 32-bit fetches per clock
— Eight-entry store buffer
— Way locking
— Supports assigning cache as instruction or data only on a per way basis
— Supports tag and data parity
Decouples processor performance from system memory performance
192 KB general-purpose SRAM of which 32 KB are on standby power
ECC performs single-bit correction, double-bit error detection
Enables and manages the transition of MCU from reset to user code execution in the following
configurations:
— User application can boot from internal or external Flash memory
— Download and execution of code via FlexCAN or eSCI
— User application can boot with either classic Power Architecture code or VLE code
24 orthogonal channels with double action, PWM, and modulus counter functionality
Supports all DASM and PWM modes of MIOS14 (MPC5xx)
Two selectable timebases
DMA and interrupt request support
Configurable Cache Memory, 0–32 KB
On-chip Internal Static RAM (SRAM)
Boot Assist Module (BAM)
Enhanced Modular I/O System (eMIOS)
MPC5561 Microcontroller Product Brief, Rev. 1
Freescale Semiconductor

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