dp83241 National Semiconductor Corporation, dp83241 Datasheet - Page 3

• Manufacturer Part Number: dp83241
• Description: Cdd Device Fddi Clock Distribution Device
• Manufacturer: National Semiconductor Corporation

1 0 FDDI Chip Set Overview
National Semiconductor’s FDDI chip set consists of five
components as shown in Figure 1-1 For more information
about the other devices in the chip set consult the appropri-
ate data sheets and application notes
DP83231 CRD
Clock Recovery Device
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream
Features
DP83241 CDD
Clock Distribution Device
From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices
DP83251 55 PLAYER
Physical Layer Controller
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard
Features
In
PHY Data request and PHY Data indicate port required
for concentration and dual attach stations











PHY Layer loopback test
Crystal controlled
Clock locks in less than 85 ms
4B 5B encoders and decoders
Framing logic
Elasticity Buffer Repeat Filter and Smoother
Line state detector generator
Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control operation
addition
the
DP83255
TM
TM
Device
Device
contains
TM
Device
an
additional
3
DP83261 BMAC
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard
Features
DP83265 BSI
System Interface
The BSI Device implements an interface between the Na-
tional FDDI BMAC device and a host system
Features




















All of the standard defined ring service options
Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
Supports Individual Group Short Long and External
Addressing
Generates Beacon Claim and Void frames internally
Extensive ring and station statistics gathering
Extensions for MAC level bridging
Separate management port that is used to configure and
control operation
Multi-frame streaming interface
32-bit wide Address Data path with byte parity
Programmable transfer burst sizes of 4 or 8 32-bit words
Interfaces to low-cost DRAMs or directly to system bus
Provides 2 Output and 3 Input Channels
Supports Header Info splitting
Efficient data structures
Programmable Big or Little Endian alignment
Full Duplex data path allows transmission to self
Comfirmation status batching services
Receive frame filtering services
Operates from 12 5 MHz to 25 MHz synchronously with
host system
TM
TM
Device
Device