lm4546a National Semiconductor Corporation, lm4546a Datasheet - Page 22

• Manufacturer Part Number: lm4546a
• Description: Ac ?97 Rev 2 Multi-channel Audio Codec With Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

www.national.com
Register Descriptions
GENERAL PURPOSE REGISTER (20h)
This register controls many miscellaneous functions imple-
mented on the LM4546A. The miscellaneous control bits
include POP which allows the DAC output to bypass the
National 3D Sound circuitry, 3D which enables or disables
the National 3D Sound circuitry, MIX which selects the MO-
NO_OUT source, MS which controls the Microphone Selec-
tion mux and LPBK which connects the output of the stereo
ADC to the input of the stereo DAC. LPBK provides a
mixed-mode analog and digital loopback path between ana-
log inputs and analog outputs.
3D CONTROL REGISTER (22h)
This read-only (0101h) register indicates, in accordance with
the AC ’97 Rev 2.1 Specification, the fixed depth and center
characteristics of the National 3D Sound stereo enhance-
ment.
POWERDOWN CONTROL / STATUS REGISTER (26h)
This read/write register is used both to monitor subsystem
readiness and also to program the LM4546A powerdown
states. The 4 LSBs indicate status and 6 of the 8 MSBs
control powerdown.
The 4 LSBs of this register indicate the status of the 4 audio
subsections of the codec: Reference voltage, Analog mixers
and amplifiers, DAC section, ADC section. When the "Codec
Ready" indicator bit in the AC Link Input Frame (SDATA_IN:
slot 0, bit 15) is a "1", it indicates that the AC Link and AC ’97
registers are in a fully operational state and that control and
status information can be transferred. It does not indicate
that the codec is ready to send or receive audio PCM data or
to pass signals through the analog I/O and mixers. To deter-
mine that readiness, the Controller must check that the 4
LSBs of this register are set to “1” indicating that the appro-
priate audio subsections are ready.
The powerdown bits PR0 – PR5 control internal subsections
of the codec. They are implemented in compliance with AC
’97 Rev 2 to support the standard device power manage-
ment states D0 – D3 as defined in the ACPI and PCI Bus
Power Management specification.
PR0 controls the powerdown state of the ADC and associ-
ated sampling rate conversion circuitry. PR1 controls power-
down for the DAC and the DAC sampling rate conversion
circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,
National 3D Sound, Mono Out, Line Out). PR3 powers down
V
powers down the AC Link digital interface – see Figure 8 for
REF
Default: 0000h
LPBK
POP
MIX
BIT
MS
3D
in addition to all the same mixer circuits as PR2. PR4
PCM Out Path:
National 3D Sound:
Mono output select:
Mic select:
ADC/DAC Loopback: *0 = No Loopback
Function
*0 = 3D allowed
*0 = off
*0 = Mix
*0 = MIC1
1 = 3D bypassed
1 = on
1 = Mic
1 = MIC2
1 = Loopback
(Continued)
22
signal powerdown timing. PR5 disables internal clocks. PR6
and PR7 are not used.
EXTENDED AUDIO ID REGISTER (28h)
This read-only register identifies which AC ’97 Extended
Audio features are supported. The LM4546A features VRA
(Variable Rate Audio) and ID1, ID0 (Multiple Codec support).
VRA is indicated by a "1" in bit 0. The two MSBs, ID1 and
ID0, show the current Codec Identity as defined by the
Identity pins ID1#, ID0# (pins 46 and 45). Note that the
external logic connections to ID1#, ID0# (pins 46 and 45) are
inverse in polarity to the value of the Codec Identity (ID1,
ID0) held in bits D15, D14. Codec mode selections are
shown in the table below.
EXTENDED AUDIO STATUS/CONTROL REGISTER
(2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4546A. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
NC/DV
NC/DV
Default: 000Xh
Default: 0000h
Pin 46
(ID1#)
GND
GND
BIT#
BIT#
VRA
BIT
10
11
12
13
14
15
0
1
2
3
8
9
DD
DD
NC/DV
NC/DV
Pin 45
*0 = VRA off (Frame-rate sampling)
(ID0#)
GND
GND
1 = VRA on
ADC
DAC
REF
ANL
PR0
PR1
PR2
PR3
PR4
PR5
PR6
PR7
BIT
BIT
DD
DD
D15,28h
Not Used
Not Used
(ID1)
1 = ADC section ready to
1 = DAC section ready to
1 = Analog mixers ready
1 = V
1 = Powerdown ADCs and
1 = Powerdown DACs
1 = Powerdown Analog Mixer
1 = Powerdown Analog Mixer
1 = Powerdown AC Link digital
1 = Disable Internal Clock
0
0
1
1
Function: Powerdown
transmit data
accept data
Record Select Mux
(V
(V
interface (BIT_CLK off)
Function
REF
Function: Status
REF
REF
D14,28h
(ID0)
is up to nominal level
0
1
0
1
still on)
off)
Codec Identity
Primary
Secondary 1
Secondary 2
Secondary 3
Mode