tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 5

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

Programmable Functions
CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to the Control
Register is as shown in Table 1. The second byte has the
following bit functions:
Note 4: state at power-on initialization.
Master Clock Frequency Selection
A Master clock must be provided to COMBO II for operation
of the filter and coding/decoding functions. The MCLK fre-
quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with
BCLK. Bits F
initialization to select the correct internal divider.
Coding Law Selection
Bits “MA” and “IA” in Table 2 permit the selection of µ255
coding or A-law coding, with or without even bit inversion.
Analog Loopback
Analog Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. In the
analog loopback mode, the Transmit input VF
F
7
0
0
1
1
1
F
TABLE 2. Control Register Byte 2 Functions
Bit Number and Name
6
0
1
0
1
0
MA IA DN DL AL PP
5
0
1
1
1
X
4
0
1
and F
3
0
1
0
2
0
1
0
(see Table 2) must be set during
1
0
X
1
0
0 Power Amp
1 Power Amp
MCLK = 512 kHz
MCLK = 1.536 MHz
MCLK = 2.048 MHz
(Note 4)
MCLK = 4.096 MHz
Select µ255 Law
(Note 4)
A-Law, Including
A-Law, No Even Bit
Delay Data Timing
Non-Delayed
4)
Normal Operation
(Note 4)
Digital Loopback
Analog Loopback
(Note 4)
or 1.544 MHz
Even Bit
Inversion
Inversion
Data Timing (Note
Enabled in PDN
Disabled in PDN
Function
(Continued)
X
I is isolated
5
from the input pin and internally connected to the VF
output, forming a loop from the Receive PCM Register back
to the Transmit PCM Register. The VF
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Digital Loopback
Digital Loopback mode is entered by setting the “AL” and
“DL” bits in the Control Register as shown in Table 2. This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at D
decoding continues and analog output appears at VF
output can be disabled by programming ‘No Output’ in the
Receive Gain Register (see Table 8).
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3. For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3076, bits 2 and 3 should
always be programmed as “1” (outputs).
Bits L
the LDR with the L bits in the second byte set as follows:
INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4. Latches configured as inputs will sense
the state applied by an external source, such as the Off-
Hook detect output of a SLIC. All bits of the ILR, i.e. sensed
inputs and the programmed state of outputs, can be read
back in the 2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first
followed immediately by the Latch Direction Register.
X = Don’t Care
TABLE 3. Byte 2 Functions of Latch Direction Register
D
L
7
7
0
0
3
–L
TABLE 4. Interface Latch Data Bit Order
0
D
L
6
6
must be set by writing the specific instruction to
1
1
L
n
0
1
Bit
L
D
5
5
2
2
Byte 2 Bit Number
Bit Number
D
L
4
4
3
3
D
3
1
3
4
R
O pin remains active,
IL Direction
D
2
1
2
Output
5
Input
X
X
1
1
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X
1. PCM
R
0. The
X
X
0
0
R
O