tp3076 National Semiconductor Corporation, tp3076 Datasheet - Page 9

• Manufacturer Part Number: tp3076
• Description: Combo Ii Programmable Pcm Codec/filter For Isdn And Digital Phone Applications
• Manufacturer: National Semiconductor Corporation

DIGITAL INTERFACES
V
V
V
V
I
I
I
ANALOG INTERFACES
I
R
VOS
RL
CL
RO
VOS
POWER DISSIPATION
I
I
I
I
I
I
Symbol
IL
IH
OZ
VFXI
CC
BB
CC
BB
CC
BB
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Electrical Characteristics
Unless otherwise noted, limits printed in BOLD characters are guaranteed for V
+70˚C by correlation with 100% electrical testing at T
tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V
T
IL
IH
OL
OH
VFXI
V
Voltage at VF
Voltage at Any Digital Input
A
VFRO
VFRO
0
1
2
0
1
2
VFRO
CC
X
R
= 25˚C.
to GND
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Current in
High Impedance
State (TRI-STATE )
Input Current, VF
Input Resistance
Input Offset Voltage
Applied at VF
Load Resistance
Load Capacitance
Output Resistance
Output Offset Voltage
at V
Power Down Current
Power Down Current
Power Up Current
Power Up Current
Power Down Current
Power Down Current
FRO
X
I
Parameter
X
I
X
I
V
V
CC
CC
All Digital Inputs (DC Meas.)
All Digital Inputs (DC Meas.) (Note 13)
D
All Other Digital Outputs, I
D
All Other Digital Outputs (except TS
All Digital Outputs, I
Any Digital Input, GND
Any Digital Input, except MR, V
MR Only
D
IL3–IL0 when Selected as Inputs
GND
−3.3V
−3.3V
Transmit Gain = 0 dB
Transmit Gain = 25.40 dB
Receive Gain = 0 dB
Receive Gain = −0.5 dB
Receive Gain = −1.2 dB
RL
CL
Steady Zero PCM Code Applied to D
Alternating
D
CCLK, CI, CO = 0.4V, CS = 2.4V
Interface Latches Set as Outputs with No Load,
All Other Inputs Active, Power Amp Disabled
As Above
CCLK, CI, CO = 0.4V, CS = 2.4V
No Load on Power Amp
Interface Latches Set as Outputs with No Load
As Above
As Above, Power Amp Enabled
As Above, Power Amp Enabled
+0.5V to GND −0.5V
X
X
X
R
+0.5V to V
1, TS
1 and CO, I
1, TS
VFRO
VFRO
1, Maximum Receive Gain
<
<
<
X
X1
V
≥ 300Ω
from VF
VF
VF
1, and CO, I
OUT
(Note 12)
and CO
±
X
X
BB
I
I
Zero PCM Code Applied
<
L
<
<
−0.5V
= −3.2 mA,
A
R
V
3.3V
3.3V
O to GND
CC
= 25˚C. All other limits are assured by correlation with other production
7V
L
Conditions
= −100 µA
L
= 3.2 mA,
<
V
L
9
IN
= 1 mA
<
Storage Temperature Range
V
Current at VF
Current at Any Digital Output
Lead Temperature
IH
BB
V
(Soldering, 10 sec.)
IL
<
to GND
X
V
), I
R
IN
1
L
<
= −1 mA
CC
V
CC
R
0
= +5V
±
5%, V
V
CC
−200
−1.0
Min
−10
−10
−10
−10
600
300
15k
2.0
2.4
1.0
BB
− 0.5
= −5V
CC
−0.1
−8.0
−2.0
Typ
1.0
0.1
8.0
2.0
= +5V, V
±
−65˚C to +150˚C
5%; T
−11.0
Max
−0.3
11.0
−3.0
100
200
200
200
0.7
0.4
1.0
3.0
0.6
3.0
A
10
10
10
10
www.national.com
BB
±
= 0˚C to
±
100 mA
= −5V,
50 mA
300˚C
−7V
Units
MΩ
mV
mV
mV
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
pF
Ω
Ω
V
V
V
V
V