at83c5122 ATMEL Corporation, at83c5122 Datasheet - Page 159
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at83c5122
Manufacturer Part Number
at83c5122
Description
At83c5123 C51 Microcontroller With Usb And Smart Card Reader Interfaces
Manufacturer
ATMEL Corporation
Datasheet
1.AT83C5122.pdf
(213 pages)
- Current page: 159 of 213
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Interrupt System
Introduction
Interrupt System
Description
4202E–SCR–06/06
The AT8xC5122/23 implements an interrupt controller with 15 inputs but only 9 are used
for :
Each of the interrupt sources can be individually enabled or disabled by setting or clear-
ing a bit in the Interrupt Enable registers (Table 98 on page 162 and Table 99 on page
163). These registers also contain a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority lev-
els by setting or clearing a bit in the Interrupt Priority Low registers (Table 101 on page
164 and Table 103 on page 166) and in the Interrupt Priority High register (Table 102 on
page 165 and Table 105 on page 168) shows the bit values and priority levels associ-
ated with each combination.
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced first. Thus within each priority level there is a second priority structure deter-
mined by the polling sequence.
Table 97. Priority Level Bit Values
–
–
–
–
–
–
–
two external interrupts (INT0 and INT1)
two timer interrupts (timers 0, 1),
the UART interface
the SPI interface
the keyboard interface
the USB interface
the Smart Card Interface.
IPH.x
0
0
1
1
IPL.x
0
1
0
1
AT8xC5122/23
Interrupt Level Priority
3 (Highest)
0 (Lowest)
1
2
159
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