mc33411a Freescale Semiconductor, Inc, mc33411a Datasheet - Page 28

• Manufacturer Part Number: mc33411a
• Description: 900 Mhz Analog Cordless Phone Baseband With Compander
• Manufacturer: Freescale Semiconductor, Inc

Transmit and Receive (LO1) PLL Sections
respectively) are designed to be part of a 900 MHz system. In
a typical application the Transmit PLL section will be set up to
generate the transmit frequency, and the Receive PLL
section will be set up to generate the LO1 frequency. The two
sections are identical, and function independently. External
requirements for each include a low–pass filter, a 900 MHz
VCO, and a 64/65 or 128/129 dual modulus prescaler.
dual modulus prescaler, and then input to the MC33411 (at
Pin 8 or 2). That frequency is then further reduced by the
programmable 13–bit counter (bits 1/19–7 or 2/19–7), and
provided to one side of the Phase Detector, where it is
compared with the PLL reference frequency. The output of
the phase detector (at Pin 6 or 4) is a Three–State charge
pump which drives the VCO through the low–pass filter. Bits
1/20 and 2/20 set the gain of each of the two charge pumps
to either 100/2π µA/radian or 400/2π µA/radian. The polarity
of the two phase detector outputs is set with bits 1/21 and
2/21. If the bit = 0, the appropriate PLL is configured to
operate with a non–inverting low–pass filter/VCO
combination. If the low–pass filter/VCO combination is
inverting, the polarity bit should be set to 1.
be set to drive the Modulus Control input of the 64/65 or
128/129 dual modulus prescalers. The Modulus Control
outputs (Pins 9 and 1) can be set to either a voltage mode
(logic 1) or a current mode (logic 0) with bit 3/16.
following procedure is used:
28
The transmit and receive PLLs (Pins 6–9 and 1–4,
The frequency output of the VCO is to be reduced by the
The 7–bit A and A’ counters (bits 1/6–0 and 2/6–0) are to
To calculate the settings of the N and A registers, the
Frequency
10.24 MHz
11.15 MHz
Crystal
Crystal
12 MHz
MCU Clk Bit #16
0
0
0
0
1
1
1
1
5.575 MHz
5.12 MHz
6.0 MHz
2.0
4.096 MHz
4.46 MHz
4.8 MHz
2.5
Table 5. MCU Clock Divider Programming
Table 6. MCU Clock Divider Frequencies
MCU Clk Bit #15
3.413 MHz
3.717 MHz
4.0 MHz
3.0
0
0
1
1
0
0
1
1
MC33411A/B
2.788 MHz
2.56 MHz
3.0 MHz
Clock Output Divider
4.0
where: f VCO = the VCO frequency
internal PLL reference frequency is 50 kHz, then the
equations yield:
A register setting is 24 (001 1000).
For example, if the VCO is to provide 910 MHz, and the
The N register setting is 284 (0 0001 0001 1100), and the
f
Nt
A = Remainder of Equation 2
f
P
VCO
PLL
2.048 MHz
MCU Clk Bit #14
2.23 MHz
2.4 MHz
f PLL = the PLL Reference Frequency set within
P = the smaller divisor of the dual modulus
N = the whole number portion is the setting for the
A = the setting for the A (or A’) counter within the
(decimal part of N x P)
5.0
N
Nt (Nt must be an integer)
prescaler (64 for a 64/65 prescaler)
N (or N’) counter within the MC33411
MC33411
0
1
0
1
0
1
0
1
Nt
N
A
the MC33411
0.375 x 64
18, 200
512 kHz
557 kHz
600 kHz
910 x 10 6
50 x 10 3
64
MOTOROLA RF/IF DEVICE DATA
20
284.375
Clk Out Divider Value
128 kHz
139 kHz
150 kHz
24
18, 200
80
312.5
2.0
3.0
4.0
5.0
2.5
20
80
32.768 kHz
35.68 kHz
38.4 kHz
312.5
(1)
(2)
(3)