mc33411a Freescale Semiconductor, Inc, mc33411a Datasheet - Page 36

• Manufacturer Part Number: mc33411a
• Description: 900 Mhz Analog Cordless Phone Baseband With Compander
• Manufacturer: Freescale Semiconductor, Inc

b. Read Operation:
1. The Enable line is taken high.
2. Five bits are entered:
3. The Enable line is taken low. At this transition, the address
4. While maintaining the Enable line low, the data is read out.
5. The full contents of the register are then read out (MSB first,
6. After the last clock pulse, the Enable line is to be taken high
7. The Enable line must then be kept low until the next
Power Supply/Power Saving Modes
range from 2.7 to 5.5 V. All V CC pins must be within 0.5 V of
each other, and each must be bypassed. It is recommended
a ground plane be used, and all leads to the MC33411 be as
short and direct as possible. To reduce the possibility of
device latch–up, it is highly recommended that the Audio,
Synthesizer and RF V CC portions of the chip be isolated from
the main supply through 10 to 25 Ω resistors (see the
Evaluation PCB Schematic, Figure 54). This also provides
RF–to–Audio noise isolation. The supply and ground pins are
distributed as follows:
1. Pin 23 provides power to the audio section. Pin 40 is the
2. Pin 28 provides power to the speaker amplifier section.
36
The power supply voltage, applied to all V CC pins, can
– To read the output bits (bits 5/23–12), or the contents of
– The first bit must be a 1 to indicate a Read operation.
– The next four bits identify the register address
is latched in and decoded, and the contents of the selected
register is loaded into the 24–bit output shift register. At this
point, the Data line (Pin 12) is still an input.
The first clock rising edge will change the Data line to an
output, and the MSB will be present on this line.
LSB last) with a total of 24 clock rising edges, including the
one in step 4 above. It is recommended that the MCU read
the bits after the clock’s falling edge.
and then low. The falling edge of this pulse returns the Data
Pin to be an input. The clock line must be at a logic low and
must not transition in either direction during this Enable
pulse.
communication.
ground pin.
Pin 31 is the ground pin.
any register, the following sequence is required (see
Figure 53):
(0001–0111). The MSB is entered first.
Enable
Clock
Data
4–Bit Address
Sets Data Pin
to Output
Figure 53. Reading Data from the MC33411
Latch Address and Load
Data into Shift Register
MSB
1
MC33411A/B
2
3
3. Pin 3 provides power to the Rx PLL section. Pin 5 is the
4. Pin 7 provides power to the Tx PLL section, and the MCU
5. Pin 42 provides power to the 2nd LO section. Pins 46 and 48
6. Pin 14 is the ground pin for the digital circuitry. Power for the
disabled by using bits 5/7–0 and 6/7 (setting a bit to 1
disables the section).
1. Reference Oscillator Disable (bit 5/0) – The reference
2. Tx PLL Disable (bit 5/1) – The 13–bit and 7–bit counters,
3. Rx PLL Disable (bit 5/2) – The 13–bit and 7–bit counters,
4. LO2 PLL Disable (bit 5/3) – The VCO, 14–bit counter,
5. Power Amplifier Disable (bit 5/4) – The two speaker
6. Rx Audio Path Disable (bit 5/5) – The anti–aliasing filter,
7. Tx Audio Path Disable (bit 5/6) – Disables the microphone
8. Low Battery/RSSI Measurement Disable (bit 5/7) – Both
9. Data Slicer Disable (bit 5/8) – The data slicer is disabled
10.
PLLs are disabled (bits 5/1–3 = 1).
24–Bit Data from MC33411
To conserve power, various sections can be individually
Note: The 12–bit reference counter is disabled if the three
ground pin.
interface. Pin 5 is the ground pin.
are the ground pins.
digital circuitry is derived from Pin 23.
oscillator at Pins 15 and 16 is disabled, thereby denying a
clock to the three PLLs and the switched capacitor filters.
This function is not available on the “B” version.
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 6 will be in a
Hi–Z state.
input buffer, phase detector, and modulus control blocks
are disabled. The charge pump output at Pin 4 will be in a
Hi–Z state.
output buffer, and phase detector are disabled. The charge
pump output at Pin 47 will be in a Hi–Z state.
amplifiers are disabled. Their outputs will go to a high
impedance state.
low–pass filter, and variable gain stage are disabled.
amplifier and low–pass filter.
6–bit A/Ds are disabled.
and DS Out goes to high impedance.
is disabled and the MCU Clock Output will be in a Hi–Z
state. This function is not available on the “B” version.
MCU Clock Disable (bit 6/7) – The MCU clock counter
MOTOROLA RF/IF DEVICE DATA
LSB
24
Sets Data Pin
to Input