mc33696fje/r2 Freescale Semiconductor, Inc, mc33696fje/r2 Datasheet - Page 27

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mc33696fje/r2

Manufacturer Part Number
mc33696fje/r2
Description
Mc33696 Pll Tuned Uhf Transceiver
Manufacturer
Freescale Semiconductor, Inc
Datasheet
16.2.2 Continuous Mode
Continuous mode is used to make a peak measurement on an incoming frame, without having to select a
specific pulse to be measured.
The quasi peak detector is reset by closing S1. After 7 x T
is set high. As long as RSSIC is kept high, S2 is closed, and RSSIOUT follows the peak value with a decay
time constant of 5 ms.
The ADC runs continuously, and continually updates the RSSI register. Thus, reading this register gives
the most recent conversion value, prior to the register being read. The minimum duration of the high pulse
on CONFB is 32 x T
17
This section discusses the internal registers, which are composed of two classes of bits.
All registers can be accessed by the SPI; these registers are described below.
At power-on, the POR resets all registers to a known value (in the shaded rows in the following tables).
This defines the MC33696’s default configuration.
After POR, CONFB forces a low level. Therefore, an external pullup resistor is required to avoid entering
configuration mode.
Freescale Semiconductor
RSSI Register
Configuration and command bits allow the MC33696 to operate in a suitable configuration.
Status bits report the current state of the system.
RSSIOUT
CONFB
Configuration, Command, and Status Registers
RSSIC
MOSI
MISO
S1
S2
Frozen
Open
Peak Detector
Closed
digclk
Test
5 x t
.
digclk
Figure 18. RSSI Operation in Continuous Mode
Updated
MC33696 Data Sheet, Rev. 9
CMD
Frozen
RSSI
digclk
Closed
Open
Configuration, Command, and Status Registers
, S1 is opened. S2 is closed when RSSIC
Updated
CMD
Frozen
RSSI
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