cp2200 Silicon Laboratories, cp2200 Datasheet - Page 82

• Manufacturer Part Number: cp2200
• Description: Single-chip Ethernet Controller
• Manufacturer: Silicon Laboratories

CP2200/1
82
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bits 11–10:Reserved. Read = 00b; Write = don’t care.
Bit 9:
Bit 8:
Bit 7–6:
Bit 5:
Bit 4:
Reserved ABORTD
PADMD1 PADMD0
Bit15
R/W
R/W
Bit7
Reserved. Read = 0b; Must write 0b.
ABORTD: Abort Disable Bit
0: MAC will abort when excessive delay is detected and update the transmit status vector.
1: MAC will attempt to transmit indefinitely as specified in IEEE 802.3.
EBBPD: Exponential Backoff after Back Pressure Disable Bit (Half-Duplex Only)
0: After incidentally causing a collision during back pressure, the MAC will use the exponential
backoff algorithm as specified in IEEE 802.3.
1: After incidentally causing a collision during back pressure, the MAC will immediately transmit
without using the exponential backoff algorithm.
EBD: Exponential Backoff Disable (Half-Duplex Only)
0: MAC will use the exponential backoff algorithm as specified in IEEE 802.3.
1: MAC will immediately retransmit following a collision.
RLPRE: Reject Long Preamble
0: MAC allows any length preamble as specified in IEEE 802.3.
1: MAC rejects packets with a preamble greater than 12 bytes in length.
PUREPRE: Pure Preamble Enforcement
0: No preamble checking is performed.
1: MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. Packets
with an invalid preamble will be rejected.
PADMD[1:0]: Pad Mode
Note: This bit field is ignored if PADEN is cleared to ‘0’. See Table 21 for a complete description.
PADEN: Pad Enable Bit (must be set to 0 in half-duplex operation)
Note: See Table 21 for a complete description.
CRCEN: CRC Enable Bit
Note: This bit must be set to ‘1’ if padding is enabled.
0: CRC will not be appended. Frames presented to the MAC must contain CRC.
1: CRC will be appended.
Bit14
R/W
R/W
Bit6
Indirect Register 2. MACCF: MAC Configuration Register
EBBPD
PADEN
Bit13
R/W
R/W
Bit5
CRCEN PHEADER Reserved LENCHK FLLDPLX
EBD
Bit12
R/W
R/W
Bit4
Bit11
R/W
R/W
Bit3
Rev. 1.0
Reserved
Bit10
R/W
R/W
Bit2
RLPRE
R/W
Bit9
R/W
Bit1
PUREPRE
R/W
R/W
Bit0
Bit8
Default Value
MACADDR:
0x0000
0x01